From WikiChip
Difference between revisions of "intel/core i7/i7-4850eq"
< intel‎ | core i7

(Created page with "{{intel title|i7-4850EQ}} {{mpu | name = Intel Core i7-4850EQ | image = | image size = | no image = yes | caption =...")
 
m (Bot: moving all {{mpu}} to {{chip}})
 
(14 intermediate revisions by 4 users not shown)
Line 1: Line 1:
−
{{intel title|i7-4850EQ}}
+
{{intel title|Core i7-4850EQ}}
−
{{mpu
+
{{chip
 
| name              = Intel Core i7-4850EQ
 
| name              = Intel Core i7-4850EQ
 
| image              =  
 
| image              =  
Line 6: Line 6:
 
| no image          = yes
 
| no image          = yes
 
| caption            =  
 
| caption            =  
 +
| designer          = Intel
 
| manufacturer      = Intel
 
| manufacturer      = Intel
 
| model number      = i7-4850EQ
 
| model number      = i7-4850EQ
Line 18: Line 19:
 
| locked            = Yes
 
| locked            = Yes
 
| frequency          = 1600 MHz
 
| frequency          = 1600 MHz
−
| turbo frequency    = yes
+
 
 
| turbo frequency1  = 3200 MHz
 
| turbo frequency1  = 3200 MHz
 
| turbo frequency2  = 3100 MHz
 
| turbo frequency2  = 3100 MHz
Line 24: Line 25:
 
| turbo frequency4  = 3000 MHz
 
| turbo frequency4  = 3000 MHz
 
| bus type          = DMI 2.0
 
| bus type          = DMI 2.0
−
| bus speed          = 5 GT/s
+
| bus speed          =
 +
| bus rate          = 5 GT/s
 
| clock multiplier  = 16
 
| clock multiplier  = 16
 
| s-spec            = SR17X
 
| s-spec            = SR17X
Line 38: Line 40:
 
| thread count      = 8
 
| thread count      = 8
 
| max cpus          = 1
 
| max cpus          = 1
−
| max memory        = 32 GB
+
| max memory        = 32 GiB
 +
 
  
−
| electrical        = Yes
 
 
| tdp                = 47 W
 
| tdp                = 47 W
 
| temp max          = 100 C
 
| temp max          = 100 C
  
−
| packaging          = Yes
+
|package module 1={{packages/intel/fcbga-1364}}
−
| package           = FCBGA1364
 
−
| package type      = FCBGA
 
−
| package pitch      =
 
−
| package size      = 37.5mm x 32mm x 1.65mm
 
−
| socket            = BGA1364
 
−
| socket type        = BGA
 
 
}}
 
}}
−
The '''Intel Core i7-4850EQ''' is a [[quad core]] [[64-bit architecture|64-bit]] mobile [[microprocessor]] released by [[Intel]] in 2014. The microprocessor is based on the [[Haswell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache.
+
'''Core i7-4850EQ''' is a [[quad core]] [[64-bit architecture|64-bit]] mobile [[microprocessor]] released by [[Intel]] in 2014. The microprocessor is based on the [[Haswell]] [[microarchitecture]]. This MPU includes the [[Intel Iris Pro 5200]] integrated graphic and features the 128 MB [[L4$]] {{intel|Crystal Well}} cache.
  
 
== Cache ==
 
== Cache ==
 +
{{main|intel/microarchitectures/haswell#Memory_Hierarchy|l1=Haswell § Cache}}
 
This specific microprocessor includes the [[has feature::Crystal Well]] cache.
 
This specific microprocessor includes the [[has feature::Crystal Well]] cache.
−
{{cache
+
{{cache info
−
| l1 cache           = 128 KB
+
|l1i cache=128 KiB
−
| l1 desc            =
+
|l1i break=4x32 KiB
−
| l1 inst            = 4x32 KB
+
|l1i desc=8-way set associative
−
| l1 inst desc       = 8-way set associative
+
|l1i extra=(per core, write-back)
−
| l1 data            = 4x32 KB
+
|l1d cache=128 KiB
−
| l1 data desc       = 8-way set associative
+
|l1d break=4x32 KiB
−
| l2 cache           = 1 MB
+
|l1d desc=8-way set associative
−
| l2 desc           = 4x256 KB 8-way set associative
+
|l1d extra=(per core, write-back)
−
| l3 cache           = 6 MB
+
|l2 cache=1 MiB
−
| l3 desc           = 12-way set associative
+
|l2 break=4x256 KiB
−
| l4 cache           = 128 MB
+
|l2 desc=8-way set associative
−
| l4 desc           = 16-way set associative (see {{intel|Crystal Well}})
+
|l2 extra=(per core, write-back)
 +
|l3 cache=6 MiB
 +
|l3 desc=12-way set associative
 +
|l3 extra=(shared)
 +
|l4 cache=128 MiB
 +
|l4 desc=16-way set associative
 +
|l4 extra=(see {{intel|Crystal Well}})
 
}}
 
}}
  
 
== Graphics ==
 
== Graphics ==
 
{{integrated graphic
 
{{integrated graphic
−
| gpu                = Intel Iris Pro 5200
+
| gpu                = Intel Iris Pro Graphics 5200
 
| displays          = 3
 
| displays          = 3
 
| frequency          = 200 MHz
 
| frequency          = 200 MHz
 
| max frequency      = 650 MHz
 
| max frequency      = 650 MHz
−
| max memory        = 1000 MB
+
| max memory        = 1 GiB
 
| output edp        = Yes
 
| output edp        = Yes
 
| output dp          = Yes
 
| output dp          = Yes
Line 104: Line 107:
  
 
== Features ==
 
== Features ==
−
{{mpu features
+
{{x86 features
 
| em64t    = Yes
 
| em64t    = Yes
 
| nx        = Yes
 
| nx        = Yes

Latest revision as of 15:22, 13 December 2017

Edit Values
Intel Core i7-4850EQ
General Info
DesignerIntel
ManufacturerIntel
Model Numberi7-4850EQ
Part NumberCL8064701528402
S-SpecSR17X
MarketMobile
IntroductionFebruary 20, 2014 (announced)
February 20, 2014 (launched)
ShopAmazon
General Specs
FamilyCore i7
LockedYes
Frequency1600 MHz
Turbo Frequency3200 MHz (1 core),
3100 MHz (2 cores),
3000 MHz (3 cores),
3000 MHz (4 cores)
Bus typeDMI 2.0
Bus rate5 GT/s
Clock multiplier16
Microarchitecture
MicroarchitectureHaswell
PlatformShark Bay
Core SteppingC0
Process22 nm
Word Size64 bits
Cores4
Threads8
Max Memory32 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
TDP47 W
OP Temperature – 100 C
Packaging
PackageFCBGA-1364 (BGA)
Dimension37.4 mm x 32 mm
Pitch0.7 mm
Ball Count1364
Ball CompSAC405
InterconnectBGA-1364

Core i7-4850EQ is a quad core 64-bit mobile microprocessor released by Intel in 2014. The microprocessor is based on the Haswell microarchitecture. This MPU includes the Intel Iris Pro 5200 integrated graphic and features the 128 MB L4$ Crystal Well cache.

Cache[edit]

Main article: Haswell § Cache

This specific microprocessor includes the Crystal Well cache.

Cache Info [Edit Values]
L1I$ 128 KiB
131,072 B
0.125 MiB
4x32 KiB 8-way set associative (per core, write-back)
L1D$ 128 KiB
131,072 B
0.125 MiB
4x32 KiB 8-way set associative (per core, write-back)
L2$ 1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
4x256 KiB 8-way set associative (per core, write-back)
L3$ 6 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
12-way set associative (shared)
L4$ 128 MiB
131,072 KiB
134,217,728 B
0.125 GiB
16-way set associative (see Crystal Well)

Graphics[edit]

Integrated Graphic Information
GPU Intel Iris Pro Graphics 5200
Displays 3
Frequency 200 MHz
0.2 GHz
200,000 KHz
Max frequency 650 MHz
0.65 GHz
650,000 KHz
Max memory 1 GiB
1,024 MiB
1,048,576 KiB
1,073,741,824 B
Output DisplayPort, Embedded DisplayPort, HDMI, VGA

Memory controller[edit]

Integrated Memory Controller
Type DDR3L-1333, DDR3L-1600
Controllers 1
Channels 2
ECC Support No
Max bandwidth 25,600 MB/s
Max memory 32,768 MB

Features[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/core_i7/i7-4850eq&oldid=70732"
Facts about "Core i7-4850EQ - Intel"
RDF feed
has featureCrystal Well + and integrated gpu +
integrated gpuIntel Iris Pro 5200 +
integrated gpu base frequency200 MHz (0.2 GHz, 200,000 KHz) +
integrated gpu max frequency650 MHz (0.65 GHz, 650,000 KHz) +
l2$ description4x256 KB 8-way set associative +
l3$ description12-way set associative +
l4$ description16-way set associative (see <a href="/wiki/intel/crystal_well" title="intel/crystal well">Crystal Well</a>) +