Semiconductor & Computer Engineering
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Difference between revisions of "Template:integrated memory controller"
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| style="text-align: center; background: #ffe5ff; font-size: 16px;" colspan="2" | '''Integrated Memory Controller''' | | style="text-align: center; background: #ffe5ff; font-size: 16px;" colspan="2" | '''Integrated Memory Controller''' | ||
|- | |- | ||
| − | {{#if:{{{type|}}}|{{!-}}|< | + | {{#if:{{{type|}}}|{{!-}}|<div></div>}} |
| − | {{#if:{{{type|}}}|{{!}} '''Type''' {{!}}{{!}} {{{type}}}|}} | + | {{#if:{{{type|}}}|{{!}} style="min-width: 125px;" {{!}} '''Type''' {{!}}{{!}} {{{type}}}{{#if:{{{type 1|}}}|, {{{type 1}}}|}}<!-- |
| − | {{#if:{{{controllers|}}}|{{!-}}|< | + | -->{{#if:{{{type 2|}}}|, {{{type 2}}}|}}<!-- |
| + | -->{{#if:{{{type 3|}}}|, {{{type 3}}}|}}<!-- | ||
| + | -->{{#if:{{{type 4|}}}|, {{{type 4}}}|}}<!-- | ||
| + | -->{{#if:{{{type 5|}}}|, {{{type 5}}}|}}<!-- | ||
| + | -->{{#if:{{{type 6|}}}|, {{{type 6}}}|}}<!-- | ||
| + | -->{{#if:{{{type 7|}}}|, {{{type 7}}}|}}<!-- | ||
| + | -->{{#if:{{{type 8|}}}|, {{{type 8}}}|}}<!-- | ||
| + | -->{{#if:{{{type 9|}}}|, {{{type 9}}}|}}<!-- | ||
| + | -->{{#if:{{{type 10|}}}|, {{{type 10}}}|}} |}} | ||
| + | {{#if:{{{controllers|}}}|{{!-}}|<div></div>}} | ||
{{#if:{{{controllers|}}}|{{!}} '''Controllers''' {{!}}{{!}} {{{controllers}}}|}} | {{#if:{{{controllers|}}}|{{!}} '''Controllers''' {{!}}{{!}} {{{controllers}}}|}} | ||
| − | {{#if:{{{channels|}}}|{{!-}}|< | + | {{#if:{{{channels|}}}|{{!-}}|<div></div>}} |
{{#if:{{{channels|}}}|{{!}} '''Channels''' {{!}}{{!}} {{{channels}}}|}} | {{#if:{{{channels|}}}|{{!}} '''Channels''' {{!}}{{!}} {{{channels}}}|}} | ||
| − | {{#if:{{{ecc support|}}}|{{!-}}|< | + | {{#if:{{{ecc support|}}}|{{!-}}|<div></div>}} |
{{#if:{{{ecc support|}}}|{{!}} '''ECC Support''' {{!}}{{!}} {{{ecc support}}}|}} | {{#if:{{{ecc support|}}}|{{!}} '''ECC Support''' {{!}}{{!}} {{{ecc support}}}|}} | ||
| − | {{#if:{{{max bandwidth|}}}|{{!-}}|< | + | {{#if:{{{max bandwidth|}}}|{{!-}}|<div></div>}} |
{{#if:{{{max bandwidth|}}}|{{!}} '''Max bandwidth''' {{!}}{{!}} {{{max bandwidth}}}|}} | {{#if:{{{max bandwidth|}}}|{{!}} '''Max bandwidth''' {{!}}{{!}} {{{max bandwidth}}}|}} | ||
| − | {{#if:{{{max memory|}}}|{{!-}}|< | + | {{#if:{{{bandwidth schan|}}}|{{!-}}|<div></div>}} |
| + | {{#if:{{{bandwidth schan|}}}|{{!}} '''Bandwidth (single)''' {{!}}{{!}} {{{bandwidth schan}}}|}} | ||
| + | {{#if:{{{bandwidth dchan|}}}|{{!-}}|<div></div>}} | ||
| + | {{#if:{{{bandwidth dchan|}}}|{{!}} '''Bandwidth (dual)''' {{!}}{{!}} {{{bandwidth dchan}}}|}} | ||
| + | {{#if:{{{bandwidth tchan|}}}|{{!-}}|<div></div>}} | ||
| + | {{#if:{{{bandwidth tchan|}}}|{{!}} '''Bandwidth (triple)''' {{!}}{{!}} {{{bandwidth tchan}}}|}} | ||
| + | {{#if:{{{bandwidth qchan|}}}|{{!-}}|<div></div>}} | ||
| + | {{#if:{{{bandwidth qchan|}}}|{{!}} '''Bandwidth (quad)''' {{!}}{{!}} {{{bandwidth qchan}}}|}} | ||
| + | {{#if:{{{bandwidth ochan|}}}|{{!-}}|<div></div>}} | ||
| + | {{#if:{{{bandwidth ochan|}}}|{{!}} '''Bandwidth (octa)''' {{!}}{{!}} {{{bandwidth ochan}}}|}} | ||
| + | {{#if:{{{max memory|}}}|{{!-}}|<div></div>}} | ||
{{#if:{{{max memory|}}}|{{!}} '''Max memory''' {{!}}{{!}} {{{max memory}}}|}} | {{#if:{{{max memory|}}}|{{!}} '''Max memory''' {{!}}{{!}} {{{max memory}}}|}} | ||
| − | |} | + | {{#if:{{{pae|}}}|{{!-}}|<div></div>}} |
| + | {{#if:{{{pae|}}}|{{!}} '''Physical Address Extensions''' {{!}}{{!}} {{{pae}}}|}} | ||
| + | |}<noinclude>{{documentation}} | ||
| + | </noinclude> | ||
Latest revision as of 13:10, 3 November 2016
| Integrated Memory Controller |
Code[edit]
== Memory controller ==
{{integrated memory controller
| type =
| type 2 =
| type N =
| controllers =
| channels =
| ecc support =
| max bandwidth =
| bandwidth schan =
| bandwidth dchan =
| bandwidth tchan =
| bandwidth qchan =
| max memory =
| pae =
}}