Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "amd/microarchitectures/k10"
Atomsymbol (talk | contribs) |
|||
| (One intermediate revision by one other user not shown) | |||
| Line 1: | Line 1: | ||
{{amd title|K10|arch}} | {{amd title|K10|arch}} | ||
{{microarchitecture | {{microarchitecture | ||
| − | | atype | + | |atype=CPU |
| − | | name | + | |name=K10 |
| − | | designer | + | |designer=AMD |
| − | | manufacturer | + | |manufacturer=AMD |
| − | | introduction | + | |introduction=November 11, 2007 |
| − | | phase-out | + | |phase-out=2012 |
| − | | process | + | |process=65 nm |
| − | | process 2 | + | |process 2=45 nm |
| + | |cores=1 | ||
| + | |cores 2=2 | ||
| + | |cores 3=3 | ||
| + | |cores 4=4 | ||
| + | |cores 5=6 | ||
| + | |type=Superscalar | ||
| + | |oooe=Yes | ||
| + | |renaming=Yes | ||
| + | |decode=3 | ||
|isa=x86-64 | |isa=x86-64 | ||
| − | | | + | |extension=MMX |
| − | | predecessor | + | |extension 2=SSE |
| − | | predecessor link = amd/microarchitectures/k8 | + | |extension 3=SSE2 |
| − | | successor | + | |extension 4=SSE3 |
| − | | successor link | + | |extension 5=SSE4A |
| + | |extension 6=3DNow! | ||
| + | |l1i=64 KiB | ||
| + | |l1i per=core | ||
| + | |l1d=64 KiB | ||
| + | |l1d per=core | ||
| + | |predecessor=K8 | ||
| + | |predecessor link=amd/microarchitectures/k8 | ||
| + | |successor=Bulldozer | ||
| + | |successor link=amd/microarchitectures/bulldozer | ||
| + | |succession=Yes | ||
}} | }} | ||
'''K10''' (sometimes '''10h''') was the [[microarchitecture]] developed by [[AMD]] as a successor to {{\\|K8}}. K10 was superseded by {{\\|Bulldozer}} in 2011. | '''K10''' (sometimes '''10h''') was the [[microarchitecture]] developed by [[AMD]] as a successor to {{\\|K8}}. K10 was superseded by {{\\|Bulldozer}} in 2011. | ||
Latest revision as of 15:24, 4 January 2022
| Edit Values | |
| K10 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | AMD |
| Manufacturer | AMD |
| Introduction | November 11, 2007 |
| Phase-out | 2012 |
| Process | 65 nm, 45 nm |
| Core Configs | 1, 2, 3, 4, 6 |
| Pipeline | |
| Type | Superscalar |
| OoOE | Yes |
| Reg Renaming | Yes |
| Decode | 3 |
| Instructions | |
| ISA | x86-64 |
| Extensions | MMX, SSE, SSE2, SSE3, SSE4A, 3DNow! |
| Cache | |
| L1I Cache | 64 KiB/core |
| L1D Cache | 64 KiB/core |
| Succession | |
K10 (sometimes 10h) was the microarchitecture developed by AMD as a successor to K8. K10 was superseded by Bulldozer in 2011.
Architecture[edit]
 |
This section is empty; you can help add the missing info by editing this page. |
Die Shot[edit]
| |
This section is empty; you can help add the missing info by editing this page. |
All K10 Chips[edit]
| K10 Chips | ||||||
|---|---|---|---|---|---|---|
| Model | Family | Core | Launched | Power Dissipation | Freq | Max Mem |
| Count: 0 | ||||||
See also[edit]
Facts about "K10 - Microarchitectures - AMD"
| codename | K10 + |
| core count | 1 +, 2 +, 3 +, 4 + and 6 + |
| designer | AMD + |
| first launched | November 11, 2007 + |
| full page name | amd/microarchitectures/k10 + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | AMD + |
| microarchitecture type | CPU + |
| name | K10 + |
| phase-out | 2012 + |
| process | 65 nm (0.065 μm, 6.5e-5 mm) + and 45 nm (0.045 μm, 4.5e-5 mm) + |