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(Relation to PPA)
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== Relation to PPA ==
 
== Relation to PPA ==
 
{{main|power-performance-area|l1=Power-Performance-Area (PPA)}}
 
{{main|power-performance-area|l1=Power-Performance-Area (PPA)}}
Iso-comparison plays an important role in the advertised benefits of new [[process nodes]]. When a foundry announces a new technology node, the [[Power-Performance-Area]] (PPA) benefits of this node is usually given in terms of ''iso-power'' and ''iso-performance'' in order to demonstrate the raw capabilities of the underlying transistors. For example, [[TSMC]]'s [[N16|16-nanometer FinFET]] process was said to deliver 2x the logic density along with >35% speed gain at iso-power OR >55% lower power at iso-speed over TSMC's own [[28 nm process]]. In other words, TSMC claims that, compared to their [[28 nm process]], their [[N16|16 nm process]] can deliver over 35% speed gain as the same total power consumption, or alternatively, over 55% power reduction at the same speed. The [[figure of merits]] (FOMs) used by TSMC for those values consisted of some combination of RO inverters, NAND, and NOT gates with Fan-Out 3 (FO3). It's worth noting that while TSMC highlights the two extreme points of its process node, realistically, chip designs choose a better sweet-spot in between those two extremes.
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Iso-comparison plays an important role in the advertised benefits of new [[process nodes]]. When a foundry announces a new technology node, the [[Power-Performance-Area]] (PPA) benefits of this node is usually given in terms of ''iso-power'' and ''iso-performance'' in order to demonstrate the raw capabilities of the underlying transistors. For example, [[TSMC]]'s [[N16|16-nanometer FinFET]] process was said to deliver 2x the logic density along with >35% speed gain at iso-power OR >55% lower power at iso-speed over TSMC's own [[28 nm process]]. In other words, TSMC claims that, compared to their [[28 nm process]], their [[N16|16 nm process]] can deliver over 35% speed gain at the same total power consumption, or alternatively, over 55% power reduction at the same speed. The [[figure of merits]] (FOMs) used by TSMC for those values consisted of some combination of RO inverters, NAND, and NOT gates with Fan-Out 3 (FO3). It's worth noting that while TSMC highlights the two extreme points of its process node, realistically, chip designs choose a better sweet-spot in between those two extremes.
  
 
== See also ==
 
== See also ==
 
* [[PPA]]
 
* [[PPA]]

Revision as of 21:54, 30 May 2020

The iso- prefix is used to indicate that a given difference measurement (or estimate) is reported while maintaining one or more other parameter(s) fixed.

Overview

The iso- prefix means 'equal'. The word originated from îsos in Ancient Greek which had a similar definition. The prefix is used to denote that a certain reported difference measurement or estimate was done while maintaining one or more secondary parameters fixed. In other words, an iso-comparison isolates one parameter from a number of parameters that affect each-other.

iso-comparisons are important for when different parameters may positively or negatively affect the primary parameter being compared. For example, a CPU core may deliver improved performance versus a predecessor by utilizing a more advanced process node or by making use of more advanced circuit design techniques or both. Using an iso-process comparison would demonstrate how much benefits came from the design alone.

Example

For example, "2nd-generation CPU core delivers 10% reduction in power at iso-performance and iso-process" means that the said 2nd-generation CPU core is able to achieve a reduction of 10% in its power consumption (under certain workload conditions) over the 1st-generation for identical performance level or capabilities on the same process node. In other words, this example highlights the circuit and architectural design improvements. This comparison isolates the power consumption of the core as a function of only circuit and architecture design improvements while intentionally ignoring the effects of using a different process technology.

Comparison types

  • iso-performance - A comparison that is done at a fixed performance level (e.g., at a fixed SPEC CPU2006/17 score).
  • iso-power - A comparison that is done at a fixed power level (e.g., 1W/core)
  • iso-area - A comparison that is done at a fixed physical silicon area (e.g., 1mm²/core)
  • iso-frequency - A comparison that is done at a fixed frequency (e.g., at 2 GHz for all devices)
  • iso-throughput - A comparison that is done at a fixed throughput (e.g., same memory or PCIe bandwidth)

This list is incomplete; you can help by expanding it.

Relation to PPA

Main article: Power-Performance-Area (PPA)

Iso-comparison plays an important role in the advertised benefits of new process nodes. When a foundry announces a new technology node, the Power-Performance-Area (PPA) benefits of this node is usually given in terms of iso-power and iso-performance in order to demonstrate the raw capabilities of the underlying transistors. For example, TSMC's 16-nanometer FinFET process was said to deliver 2x the logic density along with >35% speed gain at iso-power OR >55% lower power at iso-speed over TSMC's own 28 nm process. In other words, TSMC claims that, compared to their 28 nm process, their 16 nm process can deliver over 35% speed gain at the same total power consumption, or alternatively, over 55% power reduction at the same speed. The figure of merits (FOMs) used by TSMC for those values consisted of some combination of RO inverters, NAND, and NOT gates with Fan-Out 3 (FO3). It's worth noting that while TSMC highlights the two extreme points of its process node, realistically, chip designs choose a better sweet-spot in between those two extremes.

See also