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Difference between revisions of "arm holdings/microarchitectures/neoverse n2"
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{{armh title|Zeus|arch}}
 
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{{microarchitecture
 
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|atype=CPU
 
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|name=Zeus
 
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|designer=ARM Holdings
 
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|manufacturer=TSMC
 
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|introduction=2020
 
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|process=7 nm
 
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|oooe=Yes
 
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|speculative=Yes
 
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|renaming=Yes
 
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|predecessor=Ares
 
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|predecessor link=arm_holdings/microarchitectures/ares
 
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|successor=Poseidon
 
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|successor link=arm_holdings/microarchitectures/poseidon
 
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}}
 
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'''Zeus''' is the successor to {{\\|Ares}}, a high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the server market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips.
 
  
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== History ==
 
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[[File:arm server roadmap techcon 2018.jpg|thumb|right|Arm's server roadmap.]]
 
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Zeus was first announced by Drew Henry, Arm’s SVP and GM of Infrastructure Business Unit, at his TechCon 2018 keynote.
 
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== Release Dates ==
 
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Zeus is expected to show up in products around 2020.
 
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== Process Technology ==
 
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Zeus specifically designed takes advantage of the power and area advantages of the [[7 nm process|7nm+ process]].
 
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== Architecture ==
 
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{{future information}}
 
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=== Key changes from {{\\|Ares}} ===
 
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* [[7nm+ process]] (from [[7nm]])
 
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{{expand list}}
 
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== Bibliography ==
 
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* Drew Henry keynote, TechCon 2018 keynote.
 

Revision as of 17:48, 23 March 2020

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Facts about "Neoverse N2 - Microarchitectures - ARM"
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codenameNeoverse N2 +
core count4 +, 8 +, 16 +, 32 +, 64 +, 96 + and 128 +
designerARM Holdings +
first launchedSeptember 22, 2020 +
full page namearm holdings/microarchitectures/neoverse n2 +
instance ofmicroarchitecture +
instruction set architectureARMv9.0-A +
manufacturerTSMC +
microarchitecture typeCPU +
nameNeoverse N2 +
pipeline stages13 +
process7 nm (0.007 μm, 7.0e-6 mm) +