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| − | {{intel title|Sunny Cove|arch}}
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| − | {{microarchitecture
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| − | |atype=CPU
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| − | |name=Sunny Cove
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| − | |designer=Intel
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| − | |manufacturer=Intel
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| − | |introduction=2019
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| − | |process=10 nm
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| − | |cores=2
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| − | |cores 2=4
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| − | |type=Superscalar
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| − | |oooe=Yes
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| − | |speculative=Yes
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| − | |renaming=Yes
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| − | |stages min=14
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| − | |stages max=19
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| − | |isa=x86-64
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| − | |extension=MOVBE
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| − | |extension 2=MMX
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| − | |extension 3=SSE
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| − | |extension 4=SSE2
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| − | |extension 5=SSE3
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| − | |extension 6=SSSE3
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| − | |extension 7=SSE4.1
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| − | |extension 8=SSE4.2
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| − | |extension 9=POPCNT
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| − | |extension 10=AVX
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| − | |extension 11=AVX2
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| − | |extension 12=AES
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| − | |extension 13=PCLMUL
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| − | |extension 14=FSGSBASE
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| − | |extension 15=RDRND
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| − | |extension 16=FMA3
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| − | |extension 17=F16C
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| − | |extension 18=BMI
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| − | |extension 19=BMI2
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| − | |extension 20=VT-x
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| − | |extension 21=VT-d
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| − | |extension 22=TXT
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| − | |extension 23=TSX
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| − | |extension 24=RDSEED
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| − | |extension 25=ADCX
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| − | |extension 26=PREFETCHW
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| − | |extension 27=CLFLUSHOPT
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| − | |extension 28=XSAVE
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| − | |extension 29=SGX
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| − | |extension 30=MPX
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| − | |extension 31=AVX-512
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| − | |l1i=32 KiB
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| − | |l1i per=core
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| − | |l1i desc=8-way set associative
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| − | |l1d=48 KiB
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| − | |l1d per=core
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| − | |l1d desc=12-way set associative
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| − | |l2=512 KiB
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| − | |l2 per=core
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| − | |l2 desc=8-way set associative
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| − | |l3=2 MiB
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| − | |l3 per=core
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| − | |l3 desc=16-way set associative
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| − | |predecessor=Palm Cove
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| − | |predecessor link=intel/microarchitectures/palm cove
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| − | |successor=Willow Cove
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| − | |successor link=intel/microarchitectures/willow cove
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| − | }}
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| − | '''Sunny Cove''' ('''SNC''') is the successor to {{\\|Palm Cove}}, a high-performance [[10 nm]] [[x86]] core microarchitecture designed by [[Intel]] for an array of server and client products, including {{\\|Ice Lake (Client)}}, {{\\|Ice Lake (Server)}}, {{\\|Lakefield}}, and the Nervana {{nervana|NNP-I}}. The microarchitecture was developed by Intel's R&D Center (IDC) in Haifa, Israel.
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| | | | |
| − | == History ==
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| − | [[File:sunny cove roadmap.png|thumb|right|400px|Intel Core roadmap]]
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| − | Sunny Cove was originally unveiled by Intel at their 2018 architecture day. Intel originally intended for Sunny Cove to succeed {{\\|Palm Cove}} in late 2017 which was intended to be the first [[10 nm]]-based core and the proper successor to {{\\|Skylake (client)|Skylake}}. Prolonged delays and problems with their [[10 nm process]] resulted in a number of improvised derivatives of {{\\|Skylake (client)|Skylake}} including {{\\|Kaby Lake}}, {{\\|Coffee Lake}}, and {{\\|Comet Lake}}. For all practical purposes, {{\\|Palm Cove}} has been skipped and Intel has gone directly to Sunny Cove. Sunny Cove debuted in mid-2019.
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| − |
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| − | :[[File:14nm improv 10 delays.svg|500px]]
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| − |
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| − | == Process Technology ==
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| − | Sunny Cove is designed to take advantage of Intel's [[10 nm+ process]].
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| − |
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| − | == Architecture ==
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| − | === Key changes from {{\\|Palm Cove}}/{{\\|Skylake}}===
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| − | [[File:skylake - sunny cove changes block.jpg|thumb|right|Skylake to Sunny Cove changes]][[File:sunny cove enhancements.jpg|thumb|right|Sunny Cove enhancements]][[File:sunny cove buffer capacities.png|thumb|right|Sunny Cove buffers]]
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| − | * Significant [[IPC]] uplift ([[Intel]] self-reported average 18% IPC accross proxy benchmarks such as [[SPEC CPU2006]]/[[SPEC CPU2017]])
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| − | * Front-end
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| − | ** 1.5x larger µOP cache (2.25k entries, up from 1536)
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| − | ** Smarter [[prefetchers]]
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| − | ** Improved [[branch predictor]]
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| − | ** ITLB
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| − | *** Double 2M page entries (16 entries, up from 8)
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| − | ** Larger IDQ (70 µOPs, up from 64)
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| − | ** LSD can detect up to 70 µOP loops (up from 64)
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| − | * Back-end
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| − | ** Wider allocation (5-way, up from 4-way)
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| − | ** 1.6x larger ROB (352, up from 224 entries)
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| − | ** Scheduler
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| − | *** Larger scheduler (?, up from 97 entries)
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| − | *** Larger dispatch (10-way, up from 8-way)
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| − | * Execution Engine
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| − | ** Execution ports rebalanced
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| − | ** 2x store data ports (up from 1)
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| − | ** 2x store address AGU (up from 1)
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| − | ** New paired store capabilities
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| − | ** Replaced 2 generic AGUs with two load AGUs
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| − | * Memory subsystem
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| − | ** LSU
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| − | *** 1.8x more inflight loads (128, up from 72 entries)
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| − | *** 1.3x more inflight stores (72, up from 56 entries)
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| − | ** 1.5x larger L1 data cache (48 KiB, up from 32 KiB)
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| − | ** 2x larger L2 cache (512 KiB, up from 256 KiB)
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| − | *** Larger STLBs
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| − | **** Larger 1G table (1024-entry, up from 16)
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| − | **** Larger 4k table (2048 entries, up from 1536)
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| − | **** New 1,024-entry 2M/4M table
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| − | ** 5-Level Paging
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| − | *** Large virtual address (57 bits, up from 48 bits)
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| − | *** Significantly large virtual address space (128 PiB, up from 256 TiB)
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| − | {{expand list}}
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| − |
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| − | ==== New instructions ====
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| − | Sunny Cove introduced a number of {{x86|extensions|new instructions}}:
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| − | * {{x86|SHA|<code>SHA</code>}} - [[Hardware acceleration]] for SHA hashing operations
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| − | * {{x86|CLWB|<code>CLWB</code>}} - Force cache line write-back without flush
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| − | * {{x86|RDPID|<code>RDPID</code>}} - Read Processor ID
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| − | * Additional {{x86|AVX-512}} extensions:
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| − | ** {{x86|AVX512VPOPCNTDQ|<code>AVX512VPOPCNTDQ</code>}} - AVX-512 Vector Population Count Doubleword and Quadword
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| − | ** {{x86|AVX512VNNI|<code>AVX512VNNI</code>}} - AVX-512 Vector Neural Network Instructions
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| − | ** {{x86|AVX512GFNI|<code>AVX512GFNI</code>}} - AVX-512 Galois Field New Instructions
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| − | ** {{x86|AVX512VAES|<code>AVX512VAES</code>}} - AVX-512 Vector AES
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| − | ** {{x86|AVX512VBMI2|<code>AVX512VBMI2</code>}} - AVX-512 Vector Bit Manipulation, Version 2
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| − | ** {{x86|AVX512BITALG|<code>AVX512BITALG</code>}} - AVX-512 Bit Algorithms
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| − | ** {{x86|AVX512VPCLMULQDQ|<code>AVX512VPCLMULQDQ</code>}} - AVX-512 Vector Vector Carry-less Multiply
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| − | * {{x86|SSE_GFNI|<code>SSE_GFNI</code>}} - SSE-based Galois Field New Instructions
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| − | * {{x86|AVX_GFNI|<code>AVX_GFNI</code>}} - AVX-based Galois Field New Instructions
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| − | * Split Lock Detection - detection and cause an exception for split locks
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| − | * Fast Short REP MOV
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| − | Only on server parts ({{\\|Ice Lake (Server)}}):
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| − | * {{x86|TME|<code>TME</code>}} - Total Memory Encryption
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| − | * {{x86|PCONFIG|<code>PCONFIG</code>}} Platform Configuration
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| − | * {{x86|WBNOINVD|<code>WBNOINVD</code>}} Write-back and do not invalidate cache
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| − | * {{x86|ENCLV|<code>ENCLV</code>}} - SGX oversubscription instructions
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| − |
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| − | === Block diagram ===
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| − | :[[File:sunny cove block diagram.svg|950px]]
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| − | == Overview ==
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| − | Sunny Cove is Intel's microarchitecture for the CPU core which is incorporated into a number of client and server chips that succeed {{\\|Palm Cove}} (and effectively the {{\\|Skylake (client)|Skylake}} series of derivatives). Sunny Cove is just the core which is implemented in a numerous chips made by Intel including {{\\|Lakefield}}, {{\\|Ice Lake (Client)}}, {{\\|Ice Lake (Server)}}, and the [[Nervana]] {{nervana|NNP}} accelerator. Sunny Cove introduces a large set of enhancements that significantly improves the performance of legacy code and new code through the extraction of parallelism as well as new features. Those include a significantly deep [[out-of-window]] pipeline, a wider execution back-end, higher load-store bandwidth, lower effective access latencies, and bigger caches.
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| − | == Pipeline ==
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| − | Like its predecessors, Sunny Cove focuses on extracting performance and reducing power through a number of key ways. Intel builds Sunny Cove on previous microarchitectures, descendants of {{\\|Sandy Bridge}}. For the core to increase the overall performance, Intel focused on extracting additional parallelism.
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| − | ==== Broad Overview ====
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| − | At a 5,000 foot view, Sunny Cove represents the logical evolution from {{\\|Skylake}} and {{\\|Haswell}}. Therefore, despite some significant differences from the previous microarchitecture, the overall designs is fundamentally the same and can be seen as enhancements over {{\\|Skylake}} rather than a complete change.
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| − | [[File:intel common arch post ucache.svg|left|250px]]
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| − | The pipeline can be broken down into three areas: the front-end, back-end or execution engine, and the memory subsystem. The goal of the [[front-end]] is to feed the back-end with a sufficient stream of operations which it gets by [[decoding instructions]] coming from memory. The front-end has two major pathways: the [[µOPs cache]] path and the legacy path. The legacy path is the traditional path whereby variable-length [[x86]] instructions are fetched from the [[level 1 instruction cache]], queued, and consequently get decoded into simpler, fixed-length [[µOPs]]. The alternative and much more desired path is the µOPs cache path whereby a [[cache]] containing already decoded µOPs receives a hit allowing the µOPs to be sent directly to the decode queue.
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| − |
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| − | Regardless of which path an instruction ends up taking it will eventually arrive at the decode queue. The IDQ represents the end of the front-end and the [[in-order]] part of the machine and the start of the execution engine which operates [[out-of-order]].
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| − |
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| − | In the back-end, the micro-operations visit the [[reorder buffer]]. It's there where register allocation, renaming, and [[instruction retired|retiring]] takes place. At this stage a number of other optimizations are also done. From the reorder buffer, µOPs are sent to the unified scheduler. The scheduler has a number of exit ports, each wired to a set of different execution units. Some units can perform basic ALU operations, others can do multiplication and division, with some units capable of more complex operations such as various vector operations. The scheduler is effectively in charge of queuing the µOPs on the appropriate port so they can be executed by the appropriate unit.
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| − |
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| − | Some µOPs deal with memory access (e.g. [[instruction load|load]] & [[instruction store|store]]). Those will be sent on dedicated scheduler ports that can perform those memory operations. Store operations go to the store buffer which is also capable of performing forwarding when needed. Likewise, Load operations come from the load buffer. Sunny Cove features a dedicated 48 KiB level 1 data cache and a dedicated 32 KiB level 1 instruction cache. It also features a core-private 512 KiB L2 cache that is shared by both of the L1 caches.
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| − | Each core enjoys a slice of a third level of cache that is shared by all the core. For {{\\|Ice Lake (Client)}} which incorporates Sunny Cove cores, there are either [[two cores]] or [[four cores]] connected together on a single chip.
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| − | {{clear}}
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| − |
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| − | === Front-end ===
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| − | {{empty section}}
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| − |
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| − | {{work-in-progress}}
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| − |
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| − | === Back-end ===
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| − | {{empty section}}
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| − |
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| − | {{work-in-progress}}
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| − | == Die ==
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| − | === Core ===
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| − | * [[10 nm process|10nm+ process]]
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| − | * Core from an {{\\|Ice Lake (client)|Ice Lake}} SoC
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| − | * ~6.91 mm² die size
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| − | ** ~3.5 mm x ~1.97 mm
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| − | :[[File:ice lake die core.png|400px]]
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| − | :[[File:ice lake die core (annotated).png|400px]]
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| − | :[[File:ice lake die core 2.png|500px]]
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| − | === Core group ===
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| − | * [[10 nm process|10nm+ process]]
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| − | * Quad-core from an {{\\|Ice Lake (client)|Ice Lake}} SoC
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| − | * ~30.73 mm² die size
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| − | ** ~7.86 mm x ~3.91 mm
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| − | :[[File:ice lake die core group.png|class=wikichip_ogimage|700px]]
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| − | :[[File:ice lake die core group (annotated).png|700px]]
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| − | :[[File:ice lake die core group 2.png|800px]]
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| − | == Bibliography ==
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| − | * Intel Architecture Day 2018, December 11, 2018
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