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| − | {{intel title|Kaby Lake U|core}}
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| − | {{core
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| − | |name=Kaby Lake U
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| − | |image=kaby lake u (front; iris).png
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| − | |image size=250px
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| − | |caption=3-die config Iris Plus KBL-U (with OPC)
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| − | |image 2=kaby lake u (front; standard).png
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| − | |image 2 size=250px
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| − | |caption 2=2-die config KBL-U
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| − | |developer=Intel
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| − | |manufacturer=Intel
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| − | |first announced=August 30, 2016
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| − | |first launched=August 30, 2016
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| − | |isa=x86-64
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| − | |microarch=Kaby Lake
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| − | |word=64 bit
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| − | |proc=14 nm
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| − | |tech=CMOS
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| − | |clock min=1,800 MHz
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| − | |clock max=3,500 MHz
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| − | |package module 1={{packages/intel/fcbga-1356}}
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| − | |predecessor=Skylake U
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| − | |predecessor link=intel/cores/skylake u
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| − | |successor=Kaby Lake R
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| − | |successor link=intel/cores/kaby lake r
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| − | |successor 2=Coffee Lake U
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| − | |successor 2 link=intel/cores/coffee lake u
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| − | }}
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| − | '''Kaby Lake U''' ('''KBL-U''') is the name of the core for [[Intel]]'s line of low-power mobile processors based on the {{intel|Kaby Lake|l=arch}} microarchitecture serving as a successor to {{intel|Skylake U|l=core}}. These chips are primarily targeted towards light notebooks and laptops, portable all-in-ones (AiOs), minis, and conference rooms. Kaby Lake U processors are fabricated on Intel's enhanced [[14 nm lithography process|14nm+ process]] and provide {{intel|kaby_lake#Key_changes_from_Skylake|slight enhancements over|l=arch}} comparable Skylake models.
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| − | == Overview ==
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| − | Kaby Lake U based processors are a single-chip solution - the chipset is packaged in the same physical casing as the CPU in a [[multi-chip package]] (MCP). Note that some models (the Iris [[IGP]]s) are actually a 3 dice chip configuration since they incorporate an on-package cache (OPC) in addition to the hub and CPU. Communication between the separate dies are done via a lightweight On-Package Interconnect (OPI) interface, allowing for 4 GT/s transfer rate. All Kaby Lake U processors use {{intel|BGA-1356|Socket BGA-1356}} and all Iris models include 64 MiB of side cache.
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| − |
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| − | {| class="wikitable"
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| − | ! Standard !! Premium
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| − | |-
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| − | | 2-die configuration || 3-die configuration
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| − | |-
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| − | | GT2 Graphics || GT3 Graphics with OPC
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| − | |-
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| − | | [[File:kaby lake u (front; standard).png|250px]] || [[File:kaby lake u (front; iris).png|250px]]
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| − | |-
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| − | | [[File:kaby lake u (back; standard).png|250px]] || [[File:kaby lake u (back; iris).png|250px]]
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| − | |}
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| − | === Common Features ===
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| − | [[File:kaby lake u (front; iris) angled.png|right|300px]]
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| − | All Kaby Lake U processors have the following:
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| − |
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| − | * Dual-channel Memory
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| − | ** Up to LPDDR3-1866, DDR3L-1600, DDR3L-2133, and DDR4-2133
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| − | ** Up to 16-64 GiB
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| − | * 12x PCIe
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| − | * [[dual-core]] with 4 threads ({{intel|Celeron}} models only have 2 threads as they have {{intel|Hyper-Threading}} disabled)
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| − | * Everything up to AVX2 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX1, AVX2)
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| − | ** (Except for Pentium/Celeron which do not have AVX1/2)
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| − | * Support [[AHCI]], [[High Definition Audio]], 4-6x [[USB 3.0]] ports, 8-10x [[USB 2.0]] ports, 2-4x [[SATA III]], 6x [[I2C]], 3x [[UART]], 1x [[SDXC]]
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| − | * Graphics
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| − | ** {{intel|HD Graphics 610}} (Gen 9.5 LP GT1), {{intel|HD Graphics 620}} ({{intel|Gen9.5|l=arch}} GT2), or {{intel|Iris Plus Graphics 640}}/{{intel|Iris Plus Graphics 650|650}} ({{intel|Gen9.5|l=arch}} GT3e)
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| − | ** 3 independent displays supported
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| − | ** Base frequency of 350 MHz
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| − | ** Burst frequency of 1-1.15 GHz
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| − |
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| − | {{clear}}
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| − |
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| − | == Kaby Lake U Processors ==
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| − | <!-- NOTE:
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| − | This table is generated automatically from the data in the actual articles.
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| − | If a microprocessor is missing from the list, an appropriate article for it needs to be
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| − | created and tagged accordingly.
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| − |
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| − | Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
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| − | -->
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| − | {{comp table start}}
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| − | <table class="comptable sortable tc16 tc17 tc18 tc19 tc20 tc21">
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| − | <tr class="comptable-header"><th> </th><th colspan="21">List of Kaby Lake U Processors</th></tr>
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| − | <tr class="comptable-header"><th> </th><th colspan="11">Main processor</th><th colspan="3">IGP</th><th colspan="6">Major Feature Diff</th></tr>
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| − | <tr class="comptable-header"><th class="unsortable">Model</th><th>Launched</th><th data-sort-type="currency">Price</th><th>Family</th><th data-sort-type="number">C</th><th data-sort-type="number">T</th><th data-sort-type="number">L3$</th><th data-sort-type="number">L4$</th><th data-sort-type="number">TDP</th><th data-sort-type="number">Freq</th><th data-sort-type="number">Turbo</th><th data-sort-type="number">Max Mem</th><th>Name</th><th data-sort-type="number">Freq</th><th data-sort-type="number">Turbo</th><th>{{intel|turbo boost|TBT}}</th><th>HT</th><th>AVX2</th><th>TXT</th><th>TSX</th><th>vPro</th></tr>
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| − | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Kaby Lake U]]
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| − | |?full page name
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| − | |?model number
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| − | |?first launched
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| − | |?release price
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| − | |?microprocessor family
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| − | |?core count
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| − | |?thread count
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| − | |?l3$ size
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| − | |?l4$ size
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| − | |?tdp
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| − | |?base frequency#GHz
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| − | |?turbo frequency (1 core)#GHz
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| − | |?max memory#GiB
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| − | |?integrated gpu
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| − | |?integrated gpu base frequency
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| − | |?integrated gpu max frequency
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| − | |?has intel turbo boost technology 2_0
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| − | |?has simultaneous multithreading
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| − | |?has advanced vector extensions 2
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| − | |?has intel trusted execution technology
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| − | |?has transactional synchronization extensions
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| − | |?has intel vpro technology
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| − | |format=template
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| − | |template=proc table 3
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| − | |searchlabel=
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| − | |sort=microprocessor family, model number
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| − | |order=asc,asc
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| − | |userparam=22:17
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| − | |mainlabel=-
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| − | |limit=100
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| − | }}
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| − | {{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[core name::Kaby Lake U]]}}
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| − | </table>
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| − | {{comp table end}}
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| − |
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| − | == See also ==
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| − | {{intel kaby lake core see also}}
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| − | * {{intel|Skylake|l=arch}}
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| − | ** {{intel|Skylake U|l=core}}
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