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| − | {{lithography processes}}
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| − | The '''7 nanometer (7 nm) lithography process''' is a [[technology node]] semiconductor manufacturing process following the [[10 nm lithography process|10 nm process]] node. Mass production of [[integrated circuit]] fabricated using a 7 nm process begun in 2018. The process technology will be phased out by leading-edge foundries by 2020/21 timeframe where it will be replaced by the [[5 nm node]].
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| − | The term "7 nm" is simply a commercial name for a generation of a certain size and its technology, and '''does not''' represent any geometry of the transistor.
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| − | == Overview ==
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| − | First introduced by the major foundries around the [[2018]]-19 timeframe, the 7-nanometer [[process technology]] is characterized by its use of [[FinFET]] transistors with fin pitches in the 30s of nanometer and densest metal pitches in the upper 30s or low 40s of nanometers. Due to the small feature sizes, [[quad patterning]] had to be utilized for some layers. This process was introduced just as [[EUV Lithography]] became ready for mass production, therefore some foundries utilized EUV while others didn't. Note that Intel [[10 nm process]] is comparable to the foundry 7-nanometer node.
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| − |
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| − | === Density ===
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| − | In terms of raw cell-level density, the 7-nanometer node features silicon densities between 90-102 million [[transistors per square millimeter]] based on WikiChip's own analysis.
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| − |
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| − | :[[File:7nm densities.svg|700px]]
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| − |
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| − | == Industry ==
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| − | Only three companies are currently planning or developing a 5-nanometer node: [[Intel]], [[TSMC]], and [[Samsung]].
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| − | {{node comp|node=7 nm}}
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| − |
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| − | === Intel ===
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| − | ==== P1276 ====
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| − | Intel's 7-nanometer process, '''P1276''', will enter risk production at the end of 2020 and ramp in 2021. On February 8 2017 Intel announced a $7B investment in Arizona's Fab 42 which will eventually produce chips on a 7 nm process.
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| − |
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| − | Intel has not disclosed the details of the process but the company's current CEO claims it will feature a density that is 2x that of Intel's 10-nanometer node. Intel's prior CEO, Brian Krzanich, mentioned that 7-nanometer will have "2.4x the compaction ratio" of 10 nm. This puts the 7-nanometer node at around 202-250 [[transistors per square millimeter]].
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| − |
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| − | === TSMC ===
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| − | TSMC started mass production of its '''7-nanometer N7 node''' in April 2018. TSMC considers its 7-nanometer node a full node shrink over its 16-nanometer. Although TSMC has released a 10-nanometer node the year prior, the company considered its 10 nm to be a short-lived node and was intended to serve as a learning node on its way to 7. In early 2019 TSMC introduced the second version of its N7 process called '''N7P''' which provides additional performance enhancements. With the availability of [[asml/nxe|high-throughput EUV machines]] ready for mass production, TSMC introduced a third variant called '''N7+''' which uses EUV.
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| − |
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| − | ==== N7 ====
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| − | [[File:n7_overview_slide.jpg|right|thumb|N7 Overview]]
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| − | TSMC original '''7-nanometer N7 process''' was introduced in April 2018. Compared to its own [[16-nanometer technology]], TSMC claims its 7 nm node provides around 35-40% speed improvement or 65% lower power. Compared to the half-node [[N10|10 nm node]], N7 is said to provide ~20% speed improvement or ~40% power reduction. In terms of density, N7 is said to deliver 1.6x and 3.3x improvement compared to [[N10]] and [[N16]] respectively. N7 largely builds on all prior FinFET processes the company has had previously. To that end, this is a fourth-generation [[FinFET]], fifth-generation [[HKMG]], gate-last, dual gate oxide process.
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| − |
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| − | {| class="wikitable" style="text-align: center;"
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| − | |-
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| − | ! colspan="3" | N7 [[PPA]] vs. [[N16]]
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| − | |-
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| − | ! Speed @ iso-power !! Power @ iso-speed !! Density
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| − | |-
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| − | | ~30% || ~55% || ~3.3x
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| − | |-
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| − | ! colspan="3" | N7 PPA vs. [[N10]]
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| − | |-
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| − | ! Speed @ iso-power !! Power @ iso-speed !! Density
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| − | |-
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| − | | ~20% || ~40% || ~1.6x
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| − | |}
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| − |
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| − | [[File:tsmc-weff-16-10-7.svg|thumb|right|W<sub>eff</sub> for TSMC [[N16|16]], [[N10|10]], and 7 nm.]]
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| − | For N7, TSMC continued to use [[deep ultraviolet]] (DUV) 193 nm ArF Immersion lithography. The limitations of i193 dictated some of the design rules for the process. For the transistor, the gate pitch has been further scaled down to 57 nm, however, the interconnect pitch halted at the 40 nm point in order to keep patterning at the [[SADP]] point. Design rules were carefully made to stay within double patterning. Single patterning was pushed slightly further to the 76 nanometers point. The design rules for N7 are shown below.
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| − |
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| − | {| class="wikitable" style="text-align: center;"
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| − | ! colspan="4" | TSMC N7 Design Rules
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| − | |-
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| − | ! Layer !! Pitch (nm) !! Patterning !! Notes
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| − | |-
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| − | | Fin || 30 || SAQP ||
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| − | |-
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| − | | Poly || 57 || SADP ||
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| − | |-
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| − | | M0 || 40 || SADP || Mx
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| − | |-
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| − | | M1 || 40 || SADP || 1x
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| − | |-
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| − | | M2 || 40 || SADP || 1x
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| − | |-
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| − | | M3 || 40 || SADP || 1x
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| − | |-
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| − | | M4 || 40 || SADP || 1x
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| − | |-
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| − | | M5 || 76 || Single || 1.9x
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| − | |-
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| − | | M6 || 76 || Single || 1.9x
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| − | |-
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| − | | M7 || 76 || Single || 1.9x
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| − | |-
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| − | | M8 || 76 || Single || 1.9x
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| − | |-
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| − | | M9 || 76 || Single || 1.9x
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| − | |-
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| − | | M10 || 124 || Single || 3.1x
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| − | |-
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| − | | M11, M12 || 720 || Single || 18x
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| − | |}
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| − |
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| − | It's worth pointing out that the aggressive [[fin pitch]] scaling have resulted in a fairly dense [[SRAM bitcells]]. The N7 high-density [[SRAM bitcell]] is 0.027 µm².
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| − |
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| − | [[File:mss-n7-a12.jpg|right|thumb|Elements distribution of Apple's A12 SoC (MSS Corp). Cobalt contacts can be seen.]]
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| − | The transistor profile has been enhanced as well. Like [[Intel's 10 nm process]], TSMC introduced cobalt fill at the [[trench contacts]], replacing the tungsten contact. This has the effect of reducing the resistance in that area by 50%. Some of the area scaling and cost benefits were achieved through [[fin pitch]]/[[fin height|height]] [[scaling]]. Continuing to scale the fin width gives you a narrower channel while increasing the height to maintain a good effective width is done in order to improve the short channel characteristics and [[subthreshold slope]] (i.e., improved Ieff / Ceff) but it also degrades the overall parasitics. Keep in mind that overall, the CV/I [[device delay]] is still better because the [[intrinsic capacitance]] like the [[Cgate]] and [[Cov]] still scale with [[Ieff]].
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| − | Another way to visualize the effect of the width and height scaling is through the effective width. In the graph shown on the left, we plotted the effective width from TSMC 16 nanometer to the current 7-nanometer node. Compared to [[N16]], N7 has over twice the effective channel width.
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| − | Different multi-Vt devices were developed for this process with a Vt range of around 200 mV.
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| − | TSMC 7-nanometer comes in two variations - low power and high performance. Those [[standard cell|cells]] are 240 nm and 300 nm tall respectively.
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| − |
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| − | <table class="wikitable" style="text-align: center;">
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| − | <tr><th>Type</th><th>Low Power</th><th>High Performance</th></tr>
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| − | <tr><th>Fin Pitch</th><td colspan="2">30 nm</td></tr>
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| − | <tr><th>Metal</th><td colspan="2">40 nm (smallest pitch used with DP)<br>76 nm (smallest pitch used with SP)</td></tr>
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| − | <tr><th>Gate Pitch</th><td>57 nm</td><td>64 nm</td></tr>
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| − | <tr><th>Height</th><td>240 nm<br>8-fin x 30 nm</td><td>300 nm<br>10-fin x 30 nm</td></tr>
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| − | <tr><th>Tracks</th><td>6 T</td><td>7.5 T</td></tr>
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| − | </table>
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| − |
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| − | [[File:n7_cell_height.svg|500px]]
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| − | [[File:sdm855-n7-hd-hp-ieff.png|thumb|right|Qualcomm's [[Snapdragon 855]] [[Ieff]] difference between the HD and HP cells. (VLSI 2019)]]
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| − | Qualcomm reported that on its own SoC ([[Snapdragon 855]]), the high-performance cells deliver around 10-13% higher effective drive current ([[Ieff]]), albeit at the cost of being slightly leakier transistors. Based on WikiChip's own analysis, the dense cells come at around 91.2 [[MTr/mm²]] while the less dense, high-performance cells, are calculated at around 65 MTr/mm².
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| − |
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| − | {{clear}}
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| − |
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| − | ==== N7P ====
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| − | [[File:vlsi-2019-n7p-2nd-gen-perf.png|thumb|right|N7P (2nd Gen) vs N7 (1st Gen) improvements. (VLSI 2019)]]
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| − | In 2019 TSMC introduced a 2nd-generation N7 process called '''N7 Performance-enhanced''' ('''N7P'''). N7P is an optimized version of TSMC [[#N7|N7]] process. to that end, it remains a [[DUV]]-based process, keeping the same design rules and is fully IP-compatible with N7. N7P introduces [[FEOL]] and [[MOL]] optimizations which are said to translate to either 7% performance improvement at iso-power or up to 10% lower power at iso-speed.
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| − |
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| − | {| class="wikitable" style="text-align: center;"
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| − | |-
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| − | ! colspan="3" | N7 [[PPA]] vs. N7P
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| − | |-
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| − | ! Speed @ iso-power !! Power @ iso-speed
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| − | |-
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| − | | ~7% || ~10%
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| − | |}
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| − |
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| − | For their second generation process, TSMC made some additional optimizations, including fin profile optimizations, [[epitaxial|epi]] optimizations, MOL resistance optimizations, FEOL capacitance reduction, and metal gate optimizations. Additionally, at the same leakage, at high frequencies, the second-generation 7nm process has improved the Vmin by 50 mV.
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| − |
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| − | {{clear}}
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| − |
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| − | ==== N7+ ====
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| − | The '''N7+ node''' is TSMC's first process technology to adopt [[EUV lithography]]. It is unrelated to N7 nor N7P and is not IP-compatible with either, requiring re-implementation (new physical layout and validation). N7+ entered mass production in the second quarter of 2019 and uses EUV for four critical layers. Compared to TSMC N7 process, N7+ is said to deliver around 1.2x density improvement. N7+ is also said to deliver 10% higher performance at iso-power or, alternatively, up to 15% lower power at iso-performance. On paper, N7+ appears to be marginally better than N7P, albeit that comes at the cost of re-implementing the design.
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| − |
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| − | {| class="wikitable" style="text-align: center;"
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| − | |-
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| − | ! colspan="3" | N7 [[PPA]] vs. N7+
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| − | |-
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| − | ! Speed @ iso-power !! Power @ iso-speed !! Density
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| − | |-
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| − | | ~10% || ~15% || 1.2x
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| − | |}
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| − |
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| − | {{clear}}
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| − | === Samsung ===
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| − | Samsung will use EUVL for their 7nm node and thus will be the first to introduce this new technology after more than a decade of development.
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| − | On May 24 2017, Samsung released a press release of their updated roadmap. Due to delays in the introduction of EUVL, Samsung will introduce a new process called 8nm LPP, to bridge the gap between 10nm and 7nm. The process will be manufactured without the use of EUVL and will feature a slightly relaxed transistor size.
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| − | ==== 7LPE ====
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| − | ==== 7LPP ====
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| − | === GlobalFoundries ===
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| − | * '''Note:''' As of august 2018 GlobalFoundries has announced they will suspend further development of their 7nm, 5nm and 3nm process.
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| − | [[File:globalfoundries interconnect 7nm.jpg|right|350px]]
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| − | On May 30 2017, GlobalFoundries Senior Vice President and head of CMOS Business Unit, Gregg Bartlett, announced their updated roadmap. Instead of [[EUV]], the company will use multiple patterning 193i for their 7 nm node. The company is planning on first tape-out in the 2nd half of 2018 with mass production to begin in 2019. Bartlett noted that GF will switch to EUVL when it's ready.
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| − | The 7nm process features SAQP for the FEOL, and double patterning for the BEOL. GlobalFoundries claims a 2.8 times density improvement compared to their 14nm process, and a performance improvement of 40% or a 55% reduction in power consumption. Two versions of the process will be developed: a low power version for mobile applications. And a high performance version for desktop and server chips.
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| − | ==== 7LP ====
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| − | ==== 7HPC ====
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| − | == 7 nm Microprocessors==
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| − | * PEZY
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| − | ** {{pezy|PEZY-SC3}}
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| − | * MediaTek
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| − | ** {{mediatek|helio|Helio M70}}
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| − | * Apple
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| − | ** {{apple|A12}}
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| − | ** {{apple|A12X}}
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| − | ** {{apple|A13}}
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| − | * HiSilicon (Huawei)
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| − | ** {{hisilicon|kirin|990}}
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| − | ** {{hisilicon|kirin|980}}
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| − | ** {{hisilicon|kirin|810}}
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| − | * Snapdragon (Qualcomm)
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| − | ** {{qualcomm|snapdragon 855|855}}
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| − | {{expand list}}
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| − | == 7 nm Microarchitectures==
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| − | * AMD
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| − | ** {{amd|Vega 20|l=arch}}
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| − | ** {{amd|Navi|l=arch}}
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| − | ** {{amd|Zen 2|l=arch}}
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| − | ** {{amd|Zen 3|l=arch}}
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| − | * Ampere
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| − | ** {{ampere|Quicksilver|l=arch}}
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| − | * Esperanto
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| − | ** {{esperanto|ET-Minion|l=arch}}
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| − | ** {{esperanto|ET-Maxion|l=arch}}
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| − | * Intel
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| − | ** {{intel|Granite Rapids|l=arch}}
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| − | ** {{intel|Meteor Lake|l=arch}}
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| − | ** <s>{{intel|Knights Peak|l=arch}}</s>
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| − | == See also ==
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| − | * {{intel|process|Intel process technology history}}
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| − |
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| − | == Bibliography ==
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| − | * {{bib|iitc|2016|IBM, GlobalFoundries}}
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| − | * {{bib|iedm|2016|Samsung}}
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| − | * {{bib|isscc|2017|TSMC}}
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| − | * {{bib|vlsi|2019|Qualcomm, TSMC}}
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