Semiconductor & Computer Engineering
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Difference between revisions of "Template:expansions"
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<div style="background:#f9f9f9; margin: 10px 2px 10px 2px; padding: 5px; border: 1px solid #a7d7f9; display: inline-block; width: 700px;"> | <div style="background:#f9f9f9; margin: 10px 2px 10px 2px; padding: 5px; border: 1px solid #a7d7f9; display: inline-block; width: 700px;"> | ||
| − | <span style="margin: -12px -2px; float: right;">[[Special:FormEdit/ | + | <span style="margin: -12px -2px; float: right;">[[Special:FormEdit/expansion/{{FULLPAGENAME}}|<nowiki>[Edit/Modify Expansions Info]</nowiki>]]</span> |
<table> | <table> | ||
<tr> | <tr> | ||
| Line 12: | Line 12: | ||
{{#if: {{{pci revision|}}}{{{pci width|}}}{{{pci clock|}}}{{{pci lanes|}}} | <!-- | {{#if: {{{pci revision|}}}{{{pci width|}}}{{{pci clock|}}}{{{pci lanes|}}} | <!-- | ||
--><div style="width: 300px; display: inline-block;"><!-- | --><div style="width: 300px; display: inline-block;"><!-- | ||
| − | --><table | + | --><table><!-- |
--><tr><!-- | --><tr><!-- | ||
--><th style="width: 50px;">[[Conventional PCI|PCI]]</th><!-- | --><th style="width: 50px;">[[Conventional PCI|PCI]]</th><!-- | ||
--><td><!-- | --><td><!-- | ||
| − | --><table style="text-align: | + | --><table style="text-align: left;"><!-- |
| − | -->{{#if: {{{pci revision|}}} | <tr><th>Revision</th><td>{{{pci revision|}}}</td></tr> }}<!-- | + | -->{{#if: {{{pci revision|}}} | <tr><th style="width: 80px;">Revision</th><td>{{{pci revision|}}}</td></tr> }}<!-- |
| − | -->{{#if: {{{pci width|}}} | <tr><th>Width</th><td>{{{pci width|}}}</td></tr> }}<!-- | + | -->{{#if: {{{pci width|}}} | <tr><th style="width: 80px;">Width</th><td>{{{pci width|}}}</td></tr> }}<!-- |
| − | -->{{#if: {{{pci clock|}}} | <tr><th>Clock</th><td>{{{pci | + | -->{{#if: {{{pci clock|}}} | <tr><th style="width: 80px;">Clock</th><td>{{{pci clock|}}}</td></tr> }}<!-- |
| − | -->{{#if: {{{pci rate|}}} | <tr><th>Rate</th><td>{{{pci rate|}}}</td></tr> }}<!-- | + | -->{{#if: {{{pci rate|}}} | <tr><th style="width: 80px;">Rate</th><td>{{{pci rate|}}}</td></tr> }}<!-- |
| − | -->{{#if: {{{pci lanes|}}} | <tr><th>Max Lanes</th><td>{{{pci lanes}}} </td></tr> }}<!-- | + | -->{{#if: {{{pci lanes|}}} | <tr><th style="width: 80px;">Max Lanes</th><td>{{{pci lanes}}} </td></tr> }}<!-- |
| + | -->{{#if: {{{pci extra|}}} | <tr><th style="width: 80px;">Features</th><td>{{{pci extra}}} </td></tr> }}<!-- | ||
| + | --></table><!-- | ||
| + | --></td><!-- | ||
| + | --></tr><!-- | ||
| + | --></table><!-- | ||
| + | --></div> | ||
| + | }}<!-- | ||
| + | -->{{#if: {{{pcix revision|}}}{{{pcix width|}}}{{{pcix clock|}}}{{{pcix lanes|}}} | <!-- | ||
| + | --><div style="width: 300px; display: inline-block;"><!-- | ||
| + | --><table><!-- | ||
| + | --><tr><!-- | ||
| + | --><th style="width: 50px;">[[PCI-X]]</th><!-- | ||
| + | --><td><!-- | ||
| + | --><table style="text-align: left;"><!-- | ||
| + | -->{{#if: {{{pcix revision|}}} | <tr><th style="width: 80px;">Revision</th><td>{{{pcix revision|}}}</td></tr> }}<!-- | ||
| + | -->{{#if: {{{pcix width|}}} | <tr><th style="width: 80px;">Width</th><td>{{{pcix width|}}}</td></tr> }}<!-- | ||
| + | -->{{#if: {{{pcix clock|}}} | <tr><th style="width: 80px;">Clock</th><td>{{{pcix clock|}}}</td></tr> }}<!-- | ||
| + | -->{{#if: {{{pcix rate|}}} | <tr><th style="width: 80px;">Rate</th><td>{{{pcix rate|}}}</td></tr> }}<!-- | ||
| + | -->{{#if: {{{pcix lanes|}}} | <tr><th style="width: 80px;">Max Lanes</th><td>{{{pcix lanes}}} </td></tr> }}<!-- | ||
| + | -->{{#if: {{{pcix extra|}}} | <tr><th style="width: 80px;">Features</th><td>{{{pcix extra}}} </td></tr> }}<!-- | ||
--></table><!-- | --></table><!-- | ||
--></td><!-- | --></td><!-- | ||
| Line 34: | Line 54: | ||
--><th style="width: 50px;">PCIe</th><!-- | --><th style="width: 50px;">PCIe</th><!-- | ||
--><td><!-- | --><td><!-- | ||
| − | --><table style="text-align: | + | --><table style="text-align: left;"><!-- |
--><tr><th>Revision</th><td>{{{pcie revision}}}</td></tr><!-- | --><tr><th>Revision</th><td>{{{pcie revision}}}</td></tr><!-- | ||
| − | -->{{#if: {{{pcie lanes|}}} | <tr><th>Max Lanes</th><td> | + | -->{{#if: {{{pcie lanes|}}} | <tr><th style="width: 80px;">Max Lanes</th><td>[[max pcie lanes::{{{pcie lanes}}}| ]]{{{pcie lanes}}}</td></tr> }}<!-- |
| − | -->{{#if: {{{pcie config|}}} | <tr><th>Configs</th><td><!-- | + | -->{{#if: {{{pcie config|}}} | <tr><th style="width: 80px;">Configs</th><td><!-- |
-->{{{pcie config}}}<!-- | -->{{{pcie config}}}<!-- | ||
-->{{#if: {{{pcie config 2|}}}|, {{{pcie config 2}}}}}<!-- | -->{{#if: {{{pcie config 2|}}}|, {{{pcie config 2}}}}}<!-- | ||
| Line 49: | Line 69: | ||
--></table><!-- | --></table><!-- | ||
--></div> | --></div> | ||
| − | }} | + | }}<!-- |
| − | <table | + | -->{{#if: {{{usb revision|}}} | <!-- |
| − | <tr><!-- | + | --><div style="width: 300px; display: inline-block;"><!-- |
| − | -->{{#if: {{{sata revision|}}} | <th style="width: 50px;">SATA</th><td><!-- | + | --><table><!-- |
| + | --><tr><!-- | ||
| + | --><th style="width: 50px;">USB</th><!-- | ||
| + | --><td><!-- | ||
| + | --><table style="text-align: left;"><!-- | ||
| + | --><tr><th style="width: 80px;">Revision</th><td>{{{usb revision}}}{{#if: {{{usb revision 2|}}}|, {{{usb revision 2}}}}}</td></tr><!-- | ||
| + | -->{{#if: {{{usb ports|}}} | <tr><th style="width: 80px;">Ports</th><td>{{{usb ports}}}</td></tr> }}<!-- | ||
| + | -->{{#if: {{{usb rate|}}} | <tr><th style="width: 80px;">Rate</th><td>{{{usb rate}}}</td></tr> }}<!-- | ||
| + | -->{{#if: {{{usb extra|}}} | <tr><th style="width: 80px;">Features</th><td>{{{usb extra}}}</td></tr> }}<!-- | ||
| + | --></table><!-- | ||
| + | --></td><!-- | ||
| + | --></tr><!-- | ||
| + | --></table><!-- | ||
| + | --></div> | ||
| + | }}<!-- | ||
| + | -->{{#if: {{{uart|}}} | <!-- | ||
| + | --><div style="width: 300px; display: inline-block;"><!-- | ||
| + | --><table><!-- | ||
| + | --><tr><!-- | ||
| + | --><th style="width: 50px;">UART</th><!-- | ||
| + | --><td><!-- | ||
| + | --><table style="text-align: left;"><!-- | ||
| + | -->{{#if: {{{uart ports|}}} | <tr><th style="width: 80px;">Ports</th><td>{{{uart ports}}}</td></tr> }}<!-- | ||
| + | --></table><!-- | ||
| + | --></td><!-- | ||
| + | --></tr><!-- | ||
| + | --></table><!-- | ||
| + | --></div> | ||
| + | }}<!-- | ||
| + | -->{{#if: {{{sata revision|}}} | <!-- | ||
| + | --><div style="width: 300px; display: inline-block;"><!-- | ||
| + | --><table><!-- | ||
| + | --><tr><!-- | ||
| + | --><th style="width: 50px;">SATA</th><!-- | ||
| + | --><td><!-- | ||
| + | --><table style="text-align: left;"><!-- | ||
| + | --><tr><th style="width: 80px;">Revision</th><td>{{{sata revision}}}{{#if: {{{sata revision 2|}}}|, {{{sata revision 2}}}}}</td></tr><!-- | ||
| + | -->{{#if: {{{sata ports|}}} | <tr><th style="width: 80px;">Ports</th><td>{{{sata ports}}}</td></tr> }}<!-- | ||
| + | --></table><!-- | ||
| + | --></td><!-- | ||
| + | --></tr><!-- | ||
| + | --></table><!-- | ||
| + | --></div> | ||
| + | }}<!-- | ||
| + | -->{{#if: {{{lpc revision|}}} | <!-- | ||
| + | --><div style="width: 300px; display: inline-block;"><!-- | ||
--><table><!-- | --><table><!-- | ||
| − | --><tr><th>Revision</th><td>{{{ | + | --><tr><!-- |
| − | --><tr><th>Ports</th><td>{{{ | + | --><th style="width: 50px;">[[LPC Bus|LPC]]</th><!-- |
| + | --><td><!-- | ||
| + | --><table style="text-align: left;"><!-- | ||
| + | --><tr><th style="width: 80px;">Revision</th><td>{{{lpc revision}}}{{#if: {{{lpc revision 2|}}}|, {{{lpc revision 2}}}}}</td></tr><!-- | ||
| + | -->{{#if: {{{lpc ports|}}} | <tr><th style="width: 80px;">Ports</th><td>{{{lpc ports}}}</td></tr> }}<!-- | ||
--></table><!-- | --></table><!-- | ||
| − | --></td> | + | --></td><!-- |
--></tr><!-- | --></tr><!-- | ||
| − | -->{{#if: {{{ | + | --></table><!-- |
| + | --></div> | ||
| + | }}<!-- | ||
| + | -->{{#if: {{{i2c|}}} | <!-- | ||
| + | --><div style="width: 300px; display: inline-block;"><!-- | ||
--><table><!-- | --><table><!-- | ||
| − | --><tr><th> | + | --><tr><!-- |
| − | + | --><th style="width: 50px;">[[I²C]]</th><!-- | |
| + | --><td><!-- | ||
| + | --><table style="text-align: left;"><!-- | ||
| + | -->{{#if: {{{i2c ports|}}} | <tr><th style="width: 80px;">Ports</th><td>{{{i2c ports}}}</td></tr> }}<!-- | ||
--></table><!-- | --></table><!-- | ||
| − | --></td></tr> | + | --></td><!-- |
| − | </table> | + | --></tr><!-- |
| − | < | + | --></table><!-- |
| − | {{#if: {{{integrated lan|}}} | <tr><th>Integrated LAN</th><td>{{{integrated lan}}}</td></tr> }} | + | --></div> |
| − | {{#if: {{{ | + | }}<!-- |
| − | {{#if: {{{ | + | -->{{#if:{{{integrated lan|}}}{{{gp io|}}}{{{jtag|}}}|<!-- |
| − | </table> | + | --><hr><!-- |
| + | --><table><!-- | ||
| + | -->{{#if: {{{integrated lan|}}} | <tr><th>Integrated LAN</th><td>{{{integrated lan}}}</td></tr> }}<!-- | ||
| + | -->{{#if: {{{gp io|}}} | <tr><th>GP I/O</th><td>{{{gp io}}}</td></tr> }}<!-- | ||
| + | -->{{#if: {{{jtag|}}} | <tr><th>JTAG</th><td>{{{jtag}}}</td></tr> }}<!-- | ||
| + | --></table><!-- | ||
| + | -->}} | ||
</td> | </td> | ||
</tr> | </tr> | ||
</table> | </table> | ||
</div> | </div> | ||
| + | {{#subobject:io | ||
| + | |io_pcie_max_lanes={{{pcie lanes|}}} | ||
| + | |io_pcie_revision={{{pcie revision|}}} | ||
| + | |io_pcie_config={{{pcie config|}}} | ||
| + | |io_pcie_config={{{pcie config 2|}}} | ||
| + | |io_pcie_config={{{pcie config 3|}}} | ||
| + | |io_pcie_config={{{pcie config 4|}}} | ||
| + | |io_pcie_config={{{pcie config 5|}}} | ||
| + | }} | ||
Latest revision as of 13:33, 27 December 2019
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