From WikiChip
Difference between revisions of "Talk:amd/cores/picasso"
< Talk:amd

(Bot: creating talk page)
 
(PCIe lane count clarification needed.)
Line 1: Line 1:
 
{{talk header}}
 
{{talk header}}
 +
Is it 12 PCIe lanes (1x8 for GPU + 1x4 for storage) or 20 PCIe lanes (1x16 for GPU + 1x4 for storage) as does individual entries of the series insist?

Revision as of 05:43, 4 August 2019

This is the discussion page for the amd/cores/picasso page.
  • Please use this page to discuss possible errors, inconsistencies, omissions, changes, and further clarifications regarding the content of amd/cores/picasso.
  • If you are looking for a particular model that's missing, please add its name to this page.

Is it 12 PCIe lanes (1x8 for GPU + 1x4 for storage) or 20 PCIe lanes (1x16 for GPU + 1x4 for storage) as does individual entries of the series insist?