From WikiChip
Difference between revisions of "marvell/thunderx3"
(Add the lithography node) |
|||
Line 17: | Line 17: | ||
| proc 2 = | | proc 2 = | ||
| tech = CMOS | | tech = CMOS | ||
− | | tech 2 = | + | | tech 2 = 7nm FFN TSMC |
| clock min = | | clock min = | ||
| clock max = | | clock max = |
Revision as of 04:06, 28 July 2019
ThunderX3 | |
ThunderX3 | |
Developer | Marvell |
Manufacturer | TSMC |
Type | Microprocessors |
Introduction | 2019 (announced) |
ISA | ARMv8.2 |
µarch | Triton |
Word size | 64 bit 8 octets
16 nibbles |
Technology | CMOS, 7nm FFN TSMC "7nm FFN TSMC" is not in the list (BiCMOS, CMOS, Static CMOS, Dynamic CMOS, nMOS, pMOS, Bipolar, ECL, Schottky TTL, Schottky transistor, ...) of allowed values for the "technology" property.
|
Succession | |
← | |
ThunderX2 |
ThunderX3 is a family of 64-bit multi-core ARM server microprocessors planned by Marvell, succeeding the ThunderX2 line originally released by Cavium, now acquired by Marvell.
Overview
![]() |
This section is empty; you can help add the missing info by editing this page. |
Facts about "ThunderX3 - Marvell"
designer | Marvell + |
first announced | 2019 + |
full page name | marvell/thunderx3 + |
instance of | microprocessor family + |
instruction set architecture | ARMv8.2 + |
main designer | Marvell + |
manufacturer | TSMC + |
microarchitecture | Triton + |
name | ThunderX3 + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |