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Difference between revisions of "Talk:intel/microarchitectures/cascade lake"
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== DTLB 1G page translations associativity ==
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This page states that 1G page translations are fully associative. Intel's manual describes Skylake as 4-way. Is there a source for it being fully associative?

Latest revision as of 22:50, 30 May 2019

This is the discussion page for the intel/microarchitectures/cascade lake page.

DTLB 1G page translations associativity[edit]

This page states that 1G page translations are fully associative. Intel's manual describes Skylake as 4-way. Is there a source for it being fully associative?

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