Semiconductor & Computer Engineering
-
WikiChip
WikiChip
-
Architectures
Popular x86
-
Intel
- Client
- Server
- Big Cores
- Small Cores
-
AMD
Popular ARM
-
ARM
- Server
- Big
- Little
-
Cavium
-
Samsung
-
-
Chips
Popular Families
-
Ampere
-
Apple
-
Cavium
-
HiSilicon
-
MediaTek
-
NXP
-
Qualcomm
-
Renesas
-
Samsung
-
From WikiChip
Difference between revisions of "supercomputers/nersc-10"
(→Overview) |
|||
| Line 1: | Line 1: | ||
{{sc title|NERSC-10}} | {{sc title|NERSC-10}} | ||
| + | {{supercomputer}} | ||
'''NERSC-10''' (''no name given yet'') is the successor to {{\\|NERSC-9|Perlmutter}}, a planned [[exascale]] supercomputer set to be operated by [[National Energy Research Scientific Computing Center]]. | '''NERSC-10''' (''no name given yet'') is the successor to {{\\|NERSC-9|Perlmutter}}, a planned [[exascale]] supercomputer set to be operated by [[National Energy Research Scientific Computing Center]]. | ||
Revision as of 04:53, 4 February 2019
| Edit Values | |
| General Info |
NERSC-10 (no name given yet) is the successor to Perlmutter, a planned exascale supercomputer set to be operated by National Energy Research Scientific Computing Center.
Overview
NERSC-10 is a planned exascale supercomputer currently in pathfinding stages. NERSC-10 is expected to go online around the 2024 timeframe.
