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Difference between revisions of "cavium/thunderx/cn8890"
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{{main|cavium/microarchitectures/ThunderX1#Memory_Hierarchy|l1=ThunderX1§ Cache}} | {{main|cavium/microarchitectures/ThunderX1#Memory_Hierarchy|l1=ThunderX1§ Cache}} | ||
{{cache size | {{cache size | ||
− | |l1 cache= | + | |l1 cache=5280KiB |
− | |l1i cache= | + | |l1 break=48x110KiB |
+ | |l1i cache=3744KiB | ||
+ | |l1i break=48x78KiB | ||
|l1i desc=39-way set associative | |l1i desc=39-way set associative | ||
− | |l1d cache= | + | |l1i policy=write-back |
+ | |l1d cache=1536KiB | ||
+ | |l1d break=48x32KiB | ||
|l1d desc=32-way set associative | |l1d desc=32-way set associative | ||
|l1d policy=write-back | |l1d policy=write-back | ||
− | |l2 cache=16 MiB | + | |l2 cache=16 MiB |
|l2 desc=16-way set associative | |l2 desc=16-way set associative | ||
|l2 policy=write-back | |l2 policy=write-back |
Revision as of 22:20, 3 December 2018
Edit Values | |
ThunderX CN8890 | |
General Info | |
Designer | Cavium |
Manufacturer | GlobalFoundries |
Model Number | CN8890 |
Part Number | CN8890-1900BG2601-AAP-Y-G |
Market | Server |
Introduction | June 3, 2014 (announced) March 31, 2016 (launched) |
Release Price | $785 |
General Specs | |
Family | ThunderX |
Frequency | 1,900 MHz |
Bus type | CCPI |
Microarchitecture | |
ISA | ARMv8.1 (ARM) |
Microarchitecture | ThunderX2 |
Process | 28 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 48 |
Threads | 48 |
Max Memory | 1 TiB |
Multiprocessing | |
Max SMP | 2-Way (Multiprocessor) |
Cache
- Main article: ThunderX1§ Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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ThunderX_CP: public and private cloud servers.
Facts about "ThunderX CN8890 - Cavium"
base frequency | 1,900 MHz (1.9 GHz, 1,900,000 kHz) + |
bus type | CCPI + |
core count | 48 + |
designer | Cavium + |
family | ThunderX + |
first announced | June 3, 2014 + |
first launched | March 31, 2016 + |
full page name | cavium/thunderx/cn8890 + |
instance of | microprocessor + |
isa | ARMv8.1 + |
isa family | ARM + |
l1$ size | 5,280 KiB (5,406,720 B, 5.156 MiB) + |
l1d$ description | 32-way set associative + |
l1d$ size | 1,536 KiB (1,572,864 B, 1.5 MiB) + |
l1i$ description | 39-way set associative + |
l1i$ size | 3,744 KiB (3,833,856 B, 3.656 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) + |
ldate | March 31, 2016 + |
manufacturer | GlobalFoundries + |
market segment | Server + |
max cpu count | 2 + |
max memory | 1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) + |
microarchitecture | ThunderX2 + |
model number | CN8890 + |
name | ThunderX CN8890 + |
part number | CN8890-1900BG2601-AAP-Y-G + |
process | 28 nm (0.028 μm, 2.8e-5 mm) + |
release price | $ 785.00 (€ 706.50, £ 635.85, ¥ 81,114.05) + |
smp max ways | 2 + |
technology | CMOS + |
thread count | 48 + |
word size | 64 bit (8 octets, 16 nibbles) + |