Semiconductor & Computer Engineering
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'''Static [[CMOS]]''' is a [[logic gate|logic]] circuit design technique whereby the output is always strongly driven due to it always being connected to either [[VCC]] or [[GND]] (except when switching). This design is in contrast to [[Dynamic CMOS]] which relies on the temporary storage of signal using various load capacitances. | '''Static [[CMOS]]''' is a [[logic gate|logic]] circuit design technique whereby the output is always strongly driven due to it always being connected to either [[VCC]] or [[GND]] (except when switching). This design is in contrast to [[Dynamic CMOS]] which relies on the temporary storage of signal using various load capacitances. | ||
Latest revision as of 17:07, 26 November 2018
Static CMOS is a logic circuit design technique whereby the output is always strongly driven due to it always being connected to either VCC or GND (except when switching). This design is in contrast to Dynamic CMOS which relies on the temporary storage of signal using various load capacitances.
Overview[edit]
A static CMOS circuit is composed of two networks:
- pull-up network (PUN) - a set of PMOS transistors connected between Vcc and the output line
- pull-down network (PDN) - a set of NMOS transistors connected between GND and the output line
Components designed out pull-up and pull-down networks operate in a mutually exclusive way; in a steady state there is never a direct path between Vcc and GND. Devices that are made up of PUN/PDN are always strongly driven and therefore offers strong immunity from noise. When both the pull-up and pull-down networks are OFF, the result is high impedance. That state is important for memory elements, tristate bus drives, and various other components such as some multiplexers and buffers. When both the pull-up and pull-down networks are ON, the result is a crowbarred level. This result is typically an unwanted condition
| PUN OFF | PUN ON | |
|---|---|---|
| PDN OFF | high Z | 1 |
| PDN ON | 0 | crowbarred level |