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Difference between revisions of "nvidia/microarchitectures/denver"
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{{nvidia title|Denver|arch}}
 
{{nvidia title|Denver|arch}}
 
{{microarchitecture
 
{{microarchitecture
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| atype         = CPU
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|atype=CPU
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| name         = Denver
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|name=Denver
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| designer     = Nvidia
+
|designer=Nvidia
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| manufacturer = TSMC <!-- ??? -->>
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|manufacturer=TSMC
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| introduction = 2014
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|introduction=2014
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| phase-out    =
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|process=28 nm
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| process       = 28 nm
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|cores=2
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| cores         = 2
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|type=Superscalar
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| cores 2      =
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|oooe=No
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| cores N      =
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|decode=2-way
−
 
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|isa=ARMv8
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| type         = Superscalar
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|l1i=128 KiB
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| type 2        =
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|l1i per=core
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| type N        =
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|l1i desc=4-way set associative
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| oooe         = No
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|l1d=64 KiB
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| speculative  = <!-- Yes or No only -->
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|l1d per=core
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| renaming      = <!-- Yes or No only -->
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|l1d desc=4-way set associative
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| stages        = <!-- ONLY IF FIXED SIZE, otherwise use below for range -->
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|l2=2 MiB
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| stages min    =
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|l2 per=core
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| stages max    =
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|l2 desc=16-way set associative
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| decode       = 2-way
 
−
 
 
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| isa           = ARMv8
 
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| isa 2        =
 
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| isa N        =
 
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| feature      =
 
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| extension    =
 
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| extension 2  =
 
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| extension N  =
 
−
 
 
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| l1i           = 128 KiB
 
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| l1i per       = core
 
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| l1i desc     = 4-way set associative
 
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| l1d           = 64 KiB
 
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| l1d per       = core
 
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| l1d desc     = 4-way set associative
 
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| l2           = 2 MiB
 
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| l2 per       = core
 
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| l2 desc       = 16-way set associative
 
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| l3            =
 
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| l3 per        =
 
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| l3 desc      =
 
−
 
 
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| core name        =
 
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| core name 2      =
 
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| core name N      =
 
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| predecessor      =
 
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| predecessor link =
 
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| successor        =
 
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| successor link  =
 
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| successor 2      =
 
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| successor 2 link =
 
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| successor N      =
 
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| successor N link =
 
 
}}
 
}}
 
'''Denver''' is a CPU microarchitecture from [[Nvidia]] introduced in 2014, capable of executing ARMv8 code natively and with help of dynamic code optimization. Native ARM decoder can issue up to 2 instructions per cycle, and up to 7 micro-operations are started per cycle when dynamic code translation is used.
 
'''Denver''' is a CPU microarchitecture from [[Nvidia]] introduced in 2014, capable of executing ARMv8 code natively and with help of dynamic code optimization. Native ARM decoder can issue up to 2 instructions per cycle, and up to 7 micro-operations are started per cycle when dynamic code translation is used.

Revision as of 12:58, 16 June 2018

Edit Values
Denver µarch
General Info
Arch TypeCPU
DesignerNvidia
ManufacturerTSMC
Introduction2014
Process28 nm
Core Configs2
Pipeline
TypeSuperscalar
OoOENo
Decode2-way
Instructions
ISAARMv8
Cache
L1I Cache128 KiB/core
4-way set associative
L1D Cache64 KiB/core
4-way set associative
L2 Cache2 MiB/core
16-way set associative

Denver is a CPU microarchitecture from Nvidia introduced in 2014, capable of executing ARMv8 code natively and with help of dynamic code optimization. Native ARM decoder can issue up to 2 instructions per cycle, and up to 7 micro-operations are started per cycle when dynamic code translation is used.

Architecture

Denver is 7-wide superscalar. It has ARMv8 hardware decoder which can generate up to 2 micro-ops per cycle. Also it can execute up to 7 micro-ops per-cycle directly from L1i cache. Denver has 7 execution units: 1 branch, 2 integer (1 has hardware multiply module), 2 FP/NEON (128-bit), 2 Load/Store units.

Pipeline of Denver 1 has 15 stages, mispredict penalty is 13 cycles.

Stage name: IP1 IC2 IW3 IN4 IN5 SB1 SB2 EB0 EB1 EA2 ED3 EL4 EE5 ES6 EW7
Stage action: ITLB I$ Rd Way Sel Decode Fetch Q Pick Sched RF Rd Bypass Ld Addr D$ Read Bypass ALU/Execute St Addr RF wr

Dynamic Code Optimization

For often executed code optimization micro-interrupt can be generated and firmware-based optimizer is started. Using "Dynamic Profile Information" optimizer can translate ARMv8 instructions into optimized microcode sequence and save it into Optimization Cache. Then Denver will execute code directly from Optimization Cache without using hardware ARMv8 decoder. Several microcode sequences may be chained

In 2014 Nvidia listed several optimizations for the dynamic code translation:

  • Unrolls Loops
  • Renames registers
  • Reorders Loads and Stores
  • Improves control flow
  • Removes unused computation
  • Hoists redundant computation
  • Sinks uncommonly executed computation
  • Improves scheduling

Products

Denver is used in Nvidia's Tegra K1-64 (2014, 28 nm)

Denver 2 is used in Nvidia's Terga Parker (2016, 16 nm TSMC). Parker SoC (Tegra X2) also uses 4 Cortex-A57 cores.

Die

All Denver Chips

 List of all Denver Chips
 Main processorIGP
ModelLaunchedDesignerFamilyProcessCoreCTL2$L3$FrequencyMax MemDesignerNameFrequency
Count: 0


References

Retrieved from "https://en.wikichip.org/w/index.php?title=nvidia/microarchitectures/denver&oldid=79404"
Facts about "Denver - Microarchitectures - Nvidia"
RDF feed
codenameDenver +
core count2 +
designerNvidia +
first launched2014 +
full page namenvidia/microarchitectures/denver +
instance ofmicroarchitecture +
instruction set architectureARMv8 +
manufacturerTSMC +
microarchitecture typeCPU +
nameDenver +
process28 nm (0.028 μm, 2.8e-5 mm) +