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(Created page with "{{SpiNNaker}} {{chip}} == References == * Furber et al. "Overview of the SpiNNaker System Architecture" ''IEEE Transactions On Computers, Vol. 62, No. 12, December 2013''")
 
 
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{{SpiNNaker}}
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{{manu title|SpiNNaker - APT}}
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{{chip}}
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{{chip
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|chip type=neuromorphic chip
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|name=SpiNNaker multicore SoC
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|no image=Yes
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|designer=APT Advanced Processor Technologies Research Group
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|market=Artificial Intelligence
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|first launched=20th May, 2011
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|frequency=200MHz
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|isa=ARM9
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|isa family=ARM
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|microarch=ARM968
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|die area=102mm²
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|die length=10.386mm
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|die width=9.786mm
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|mcp=Yes
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|die count=2
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|core count=18
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|max cpus=1,036,800 (system)
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|max memory=128MB (chip), 7TB (system)
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|power=1W (chip), 90kW (system)
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|neuron count=1,000,000,000
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}}
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'''SpiNNaker''' ('''[[Spiking Neural Network]] Architecture''') is a research project by the Advanced Processor Technologies Research Group of the [[University of Manchester]]. In its full configuration, the system consists of 1,036,800 {{armh|ARM9|l=arch}} cores that are capable of simulating up to one billion neurons in real time.
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== Overview ==
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The SpiNNaker engine is using the ''SpiNNaker multicore System-On-Chip (SoC)'' as single nodes. Each chip contains two dies: The first die holds 18 ARM968 cores, 32kB SRAM, 64kB data tightly coupled memory (DTCM) per core, 32kB instruction tightly coupled memory (ITCM) per core, an Ethernet interface and a ''custom interconnect fabric''. The second die within the SoC holds 128MB of shared SDRAM.
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== System Components ==
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=== ARM968 ===
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=== Vectored [[Interrupt]] Controller (VIC) ===
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=== Counter/Timer units ===
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=== Ethernet ===
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=== DMA ===
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=== Memory ===
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== Routing fabric ==
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Latest revision as of 09:19, 19 May 2018

Edit Values
SpiNNaker multicore SoC
General Info
DesignerAPT Advanced Processor Technologies Research Group
MarketArtificial Intelligence
Introduction20th May, 2011 (launched)
General Specs
Frequency200MHz
Neuromorphic Specs
Neurons1,000,000,000
Microarchitecture
ISAARM9 (ARM)
MicroarchitectureARM968
Die102mm²
10.386mm × 9.786mm
MCPYes (2 dies)
Cores18
Max Memory128MB (chip), 7TB (system)
Multiprocessing
Max SMP1,036,800 (system)-Way (Multiprocessor)
Electrical
Power dissipation1W (chip), 90kW (system)

SpiNNaker (Spiking Neural Network Architecture) is a research project by the Advanced Processor Technologies Research Group of the University of Manchester. In its full configuration, the system consists of 1,036,800 ARM9 cores that are capable of simulating up to one billion neurons in real time.

Overview[edit]

The SpiNNaker engine is using the SpiNNaker multicore System-On-Chip (SoC) as single nodes. Each chip contains two dies: The first die holds 18 ARM968 cores, 32kB SRAM, 64kB data tightly coupled memory (DTCM) per core, 32kB instruction tightly coupled memory (ITCM) per core, an Ethernet interface and a custom interconnect fabric. The second die within the SoC holds 128MB of shared SDRAM.

System Components[edit]

ARM968[edit]

Vectored Interrupt Controller (VIC)[edit]

Counter/Timer units[edit]

Ethernet[edit]

DMA[edit]

Memory[edit]

Routing fabric[edit]

References[edit]

  • Furber et al. "Overview of the SpiNNaker System Architecture" IEEE Transactions On Computers, Vol. 62, No. 12, December 2013
Retrieved from "https://en.wikichip.org/w/index.php?title=university_of_manchester/spinnaker&oldid=77954"
Facts about "SpiNNaker - APT - The University of Manchester"
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base frequency200 MHz (0.2 GHz, 200,000 kHz) +
core count18 +
designerAPT Advanced Processor Technologies Research Group +
die area102 mm² (0.158 in², 1.02 cm², 102,000,000 µm²) +
die count2 +
die length10.386 mm (1.039 cm, 0.409 in, 10,386 µm) +
die width9.786 mm (0.979 cm, 0.385 in, 9,786 µm) +
first launchedMay 20, 2011 +
full page nameuniversity of manchester/spinnaker +
instance ofneuromorphic chip +
is multi-chip packagetrue +
isaARM9 +
isa familyARM +
ldateMay 20, 2011 +
market segmentArtificial Intelligence +
microarchitectureARM968 +
nameSpiNNaker multicore SoC +
neuron count1,000,000,000 +
smp max ways1,036,800 (system) +