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Difference between revisions of "renesas/r-car/v2h"
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{{renesas title|R-Car V2H}}
 
{{renesas title|R-Car V2H}}
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|name=R-Car V2H
 
|name=R-Car V2H
 
|image=r-car v2h.jpg
 
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'''R-Car V2H''' is high-performance embedded {{arch|64}} [[dual-core]] [[arm]] SoC designed by [[Renesas]] for the automotive industry and introduced in 2014. The V2H has two {{armh|Cortex-A15}} cores operating at 1 GHz and incorporates the [[imagination technologies|Imagination]] {{imgtec|PowerVR SGX531}} [[GPU]]. This SoC supports up to DDR3-1600 memory.
 
'''R-Car V2H''' is high-performance embedded {{arch|64}} [[dual-core]] [[arm]] SoC designed by [[Renesas]] for the automotive industry and introduced in 2014. The V2H has two {{armh|Cortex-A15}} cores operating at 1 GHz and incorporates the [[imagination technologies|Imagination]] {{imgtec|PowerVR SGX531}} [[GPU]]. This SoC supports up to DDR3-1600 memory.
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Samples for the V2H were available starting September 2014 with Renesas expecting mass production to begin around October 2016 with combined production reaching a volume of 500,000 units per month by October 2017.
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== Cache ==
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{{main|arm holdings/microarchitectures/cortex-a15#Memory_Hierarchy|l1=Cortex-A15 § Cache}}
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{{cache size
 +
|l1 cache=128 KiB
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|l1i cache=64 KiB
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|l1i break=2x32 KiB
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|l1d cache=64 KiB
 +
|l1d break=2x32 KiB
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|l2 cache=1 MiB
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}}
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 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR3-1600
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|ecc=Yes
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|controllers=1
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|channels=1
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|width=32 bit
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|max bandwidth=5.96 GiB/s
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|bandwidth schan=5.96 GiB/s
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}}
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== Expansions ==
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* Flash ROM and SRAM Data bus width: 8/16 bit
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* CAN 2 channels
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* Ethernet AVB; 1000 Mbps, 100 Mbps, IEEE802.3 PHY
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== Graphics ==
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{{integrated graphics
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| gpu                = PowerVR SGX531
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| designer            = Imagination Technologies
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}}
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== Features ==
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{{arm features
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|thumb=No
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|thumb2=No
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|thumbee=No
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|vfpv1=No
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|vfpv2=No
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|vfpv3=No
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|vfpv3-d16=No
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|vfpv3-f16=No
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|vfpv4=Yes
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|vfpv4-d16=No
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|vfpv5=No
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|neon=Yes
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|trustzone=Yes
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|jazelle=No
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|wmmx=No
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|wmmx2=No
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}}
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== Block Diagram ==
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::[[File:blk rcar v2h.jpg|700px]]
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== Development Board ("BLANCHE") ==
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* 210 mm x 160 mm
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* R-Car V2H
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* 64 MiB NOR & 4 MiB SPI flash memory
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* 1 GB DDR3-DRAM-1600; 32-bit configuration
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* 6 x video inputs
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* EtherAVB (GMII/MII)
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* SD card host interfaces
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* Two CAN interfaces
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* HDMI and RGB display-out
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* switches, LEDs, I/O expansion headers
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* JTAG debug/trace connectors
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* expansion connectors
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* Five-channel low-delay H.264/JPEG decoder
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* Image recognition engines

Latest revision as of 15:32, 13 December 2017

Edit Values
R-Car V2H
r-car v2h.jpg
General Info
DesignerRenesas,
ARM Holdings
ManufacturerTSMC
Model NumberV2H
Part NumberR8A7792
MarketEmbedded
IntroductionAugust 28, 2014 (announced)
October, 2016 (launched)
General Specs
FamilyR-Car
Series2nd Gen
Frequency1,000 MHz
Microarchitecture
ISAARMv8 (ARM)
MicroarchitectureCortex-A15
Core NameCortex-A15
Process28 nm
TechnologyCMOS
Word Size64 bit
Cores2
Threads2
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Vcore1.03 V
VI/O3.3 V
Packaging
PackageFCBGA-64 (BGA)
Dimension10 mm x 10 mm
Pitch0.40 mm
Ball Count64
InterconnectBGA-64

R-Car V2H is high-performance embedded 64-bit dual-core arm SoC designed by Renesas for the automotive industry and introduced in 2014. The V2H has two Cortex-A15 cores operating at 1 GHz and incorporates the Imagination PowerVR SGX531 GPU. This SoC supports up to DDR3-1600 memory.

Samples for the V2H were available starting September 2014 with Renesas expecting mass production to begin around October 2016 with combined production reaching a volume of 500,000 units per month by October 2017.

Cache[edit]

Main article: Cortex-A15 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB  
L1D$64 KiB
65,536 B
0.0625 MiB
2x32 KiB  
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
     

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-1600
Supports ECCYes
Controllers1
Channels1
Width32 bit
Max Bandwidth5.96 GiB/s
6,103.04 MiB/s
6.4 GB/s
6,399.501 MB/s
0.00582 TiB/s
0.0064 TB/s
Bandwidth
Single 5.96 GiB/s

Expansions[edit]

  • Flash ROM and SRAM Data bus width: 8/16 bit
  • CAN 2 channels
  • Ethernet AVB; 1000 Mbps, 100 Mbps, IEEE802.3 PHY

Graphics[edit]

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUPowerVR SGX531
DesignerImagination Technologies

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
VFPv4Vector Floating Point (VFP) v4 Extension
NEONAdvanced SIMD extension
TrustZoneTrustZone Security Extensions

Block Diagram[edit]

blk rcar v2h.jpg

Development Board ("BLANCHE")[edit]

  • 210 mm x 160 mm
  • R-Car V2H
  • 64 MiB NOR & 4 MiB SPI flash memory
  • 1 GB DDR3-DRAM-1600; 32-bit configuration
  • 6 x video inputs
  • EtherAVB (GMII/MII)
  • SD card host interfaces
  • Two CAN interfaces
  • HDMI and RGB display-out
  • switches, LEDs, I/O expansion headers
  • JTAG debug/trace connectors
  • expansion connectors
  • Five-channel low-delay H.264/JPEG decoder
  • Image recognition engines
Retrieved from "https://en.wikichip.org/w/index.php?title=renesas/r-car/v2h&oldid=71201"
Facts about "R-Car V2H - Renesas"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
R-Car V2H - Renesas#package +
base frequency1,000 MHz (1 GHz, 1,000,000 kHz) +
core count2 +
core nameCortex-A15 +
core voltage1.03 V (10.3 dV, 103 cV, 1,030 mV) +
designerRenesas + and ARM Holdings +
familyR-Car +
first announcedAugust 28, 2014 +
first launchedOctober 2016 +
full page namerenesas/r-car/v2h +
has ecc memory supporttrue +
instance ofmicroprocessor +
integrated gpuPowerVR SGX531 +
integrated gpu designerImagination Technologies +
io voltage3.3 V (33 dV, 330 cV, 3,300 mV) +
isaARMv8 +
isa familyARM +
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
ldateOctober 2016 +
main imageFile:r-car v2h.jpg +
manufacturerTSMC +
market segmentEmbedded +
max cpu count1 +
max memory bandwidth5.96 GiB/s (6,103.04 MiB/s, 6.4 GB/s, 6,399.501 MB/s, 0.00582 TiB/s, 0.0064 TB/s) +
max memory channels1 +
microarchitectureCortex-A15 +
model numberV2H +
nameR-Car V2H +
packageFCBGA-64 +
part numberR8A7792 +
process28 nm (0.028 μm, 2.8e-5 mm) +
series2nd Gen +
smp max ways1 +
supported memory typeDDR3-1600 +
technologyCMOS +
thread count2 +
word size64 bit (8 octets, 16 nibbles) +