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Difference between revisions of "renesas/r-car/m3 (sip)"
< renesas‎ | r-car

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{{renesas title|R-Car M3 (SiP)}}
 
{{renesas title|R-Car M3 (SiP)}}
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{{mpu
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{{chip
 
|name=R-Car M3 (SiP)
 
|name=R-Car M3 (SiP)
 
|image=r-car m3 (sip).png
 
|image=r-car m3 (sip).png
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|package module 1={{packages/renesas/fcbga-1255}}
 
|package module 1={{packages/renesas/fcbga-1255}}
 
}}
 
}}
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'''R-Car M3''' is a {{arch|64}} [[hepta-core]] [[ARM]] SoC designed by [[Renesas]] for the automotive industry and introduced in 2016. The M3 incorporates four {{armh|Cortex-A53}} cores, two {{armh|Cortex-A57}}, and an additional {{armh|Cortex-R7}} core for real-time processing. This chip supports up to dual-channel LPDDR4-3200 memory.
+
'''R-Car M3''' is a {{arch|64}} [[hepta-core]] [[ARM]] SoC designed by [[Renesas]] for the automotive industry and introduced in 2016. The M3 incorporates four {{armh|Cortex-A53}} cores, two {{armh|Cortex-A57}}, and an additional {{armh|Cortex-R7}} core for real-time processing. This chip supports up to dual-channel LPDDR4-3200 memory.  This chip incorporates the [[imagination technologies|Imagination]]'s {{imgtec|PowerVR GX6250}} [[GPU]].
  
 
This model is an [[SiP]] variant of the {{\\|M3}} which include the DDR memory on-package.
 
This model is an [[SiP]] variant of the {{\\|M3}} which include the DDR memory on-package.
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{{main|arm holdings/microarchitectures/cortex-a53#Memory_Hierarchy|arm holdings/microarchitectures/cortex-a57#Memory_Hierarchy|l1=Cortex-A53 § Cache|l2=Cortex-A57 § Cache}}
 
{{main|arm holdings/microarchitectures/cortex-a53#Memory_Hierarchy|arm holdings/microarchitectures/cortex-a57#Memory_Hierarchy|l1=Cortex-A53 § Cache|l2=Cortex-A57 § Cache}}
 
{{cache size
 
{{cache size
−
|l1 cache=544 KiB
+
|l1 cache=480 KiB
 
|l1i cache=256 KiB
 
|l1i cache=256 KiB
 
|l1i break=2x48+5x32 KiB
 
|l1i break=2x48+5x32 KiB
−
|l1d cache=288 KiB
+
|l1d cache=224 KiB
−
|l1d break=9x32 KiB
+
|l1d break=7x32 KiB
 
|l2 cache=1.5 MiB
 
|l2 cache=1.5 MiB
 
}}
 
}}
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|bandwidth dchan=11.92 GiB/s
 
|bandwidth dchan=11.92 GiB/s
 
}}
 
}}
 +
 +
== Expansions ==
 +
* USB 3.0 host interface (DRD) × 1 port (wPHY)
 +
* USB 2.0 host interface × 1 port (wPHY)
 +
* USB 2.0 host/function/OTG interface × 1 port (wPHY)
 +
* SD host interface × 4 ch (SDR104)
 +
* Multimedia card interface × 2 ch
 +
* PCI Express 2.0 (1 lane) x 2 ch
 +
* Media local bus (MLB) interface × 1 ch (3-pin interface)
 +
* Controller area network (CAN-FD support) interface × 2ch
 +
* Ethernet AVB 1.0-compatible MAC built in Interface: RGMII / Ethernet AVB (802.1BA)
 +
* I2C bus interface × 8 ch
 +
* Serial communication interface (SCIF) × 11 ch
 +
* SPI multi I/O bus controller (RPC) × 1 ch (HyperFlashTM/QSPI support)
 +
* Clock-synchronized serial interface (MSIOF) × 4 ch (SPI/IIS)
 +
* Digital radio interface (DRIF) × 4 ch
 +
 +
== Graphics ==
 +
{{integrated graphics
 +
| gpu                = PowerVR GX6250
 +
| designer            = Imagination Technologies
 +
}}
 +
 +
== Features ==
 +
{{arm features
 +
|thumb=No
 +
|thumb2=No
 +
|thumbee=No
 +
|vfpv1=No
 +
|vfpv2=No
 +
|vfpv3=No
 +
|vfpv3-d16=No
 +
|vfpv3-f16=No
 +
|vfpv4=Yes
 +
|vfpv4-d16=No
 +
|vfpv5=No
 +
|neon=Yes
 +
|trustzone=Yes
 +
|jazelle=No
 +
|wmmx=No
 +
|wmmx2=No
 +
}}
 +
 +
== Block Diagram ==
 +
:: [[File:blk rcar m3.jpg|750px]]

Latest revision as of 15:32, 13 December 2017

Edit Values
R-Car M3 (SiP)
r-car m3 (sip).png
General Info
DesignerRenesas,
ARM Holdings
ManufacturerTSMC
Model NumberM3 (SiP)
Part NumberR8J77960
MarketEmbedded
IntroductionOctober 19, 2016 (announced)
October, 2016 (launched)
General Specs
FamilyR-Car
Series3rd Gen
Microarchitecture
ISAARMv8 (ARM)
MicroarchitectureCortex-A53, Cortex-A57, Cortex-R7
Core NameCortex-A53, Cortex-A57, Cortex-R7
Process16 nm
TechnologyCMOS
Word Size64 bit
Cores7
Threads7
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Vcore0.9 V
VI/O3.3 V
Packaging
PackageFCBGA-1255 (BGA)
Dimension42.5 mm x 42.5 mm
Pitch0.80 mm
Ball Count1255
InterconnectBGA-1255

R-Car M3 is a 64-bit hepta-core ARM SoC designed by Renesas for the automotive industry and introduced in 2016. The M3 incorporates four Cortex-A53 cores, two Cortex-A57, and an additional Cortex-R7 core for real-time processing. This chip supports up to dual-channel LPDDR4-3200 memory. This chip incorporates the Imagination's PowerVR GX6250 GPU.

This model is an SiP variant of the M3 which include the DDR memory on-package.

Cache[edit]

Main articles: Cortex-A53 § Cache and Cortex-A57 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$480 KiB
491,520 B
0.469 MiB
L1I$256 KiB
262,144 B
0.25 MiB
2x48+5x32 KiB  
L1D$224 KiB
229,376 B
0.219 MiB
7x32 KiB  
L2$1.5 MiB
1,536 KiB
1,572,864 B
0.00146 GiB
     

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR4-3200
Supports ECCNo
Controllers1
Channels2
Width32 bit
Max Bandwidth11.92 GiB/s
12,206.08 MiB/s
12.799 GB/s
12,799.003 MB/s
0.0116 TiB/s
0.0128 TB/s
Bandwidth
Single 5.96 GiB/s
Double 11.92 GiB/s

Expansions[edit]

  • USB 3.0 host interface (DRD) × 1 port (wPHY)
  • USB 2.0 host interface × 1 port (wPHY)
  • USB 2.0 host/function/OTG interface × 1 port (wPHY)
  • SD host interface × 4 ch (SDR104)
  • Multimedia card interface × 2 ch
  • PCI Express 2.0 (1 lane) x 2 ch
  • Media local bus (MLB) interface × 1 ch (3-pin interface)
  • Controller area network (CAN-FD support) interface × 2ch
  • Ethernet AVB 1.0-compatible MAC built in Interface: RGMII / Ethernet AVB (802.1BA)
  • I2C bus interface × 8 ch
  • Serial communication interface (SCIF) × 11 ch
  • SPI multi I/O bus controller (RPC) × 1 ch (HyperFlashTM/QSPI support)
  • Clock-synchronized serial interface (MSIOF) × 4 ch (SPI/IIS)
  • Digital radio interface (DRIF) × 4 ch

Graphics[edit]

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUPowerVR GX6250
DesignerImagination Technologies

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
VFPv4Vector Floating Point (VFP) v4 Extension
NEONAdvanced SIMD extension
TrustZoneTrustZone Security Extensions

Block Diagram[edit]

blk rcar m3.jpg
Retrieved from "https://en.wikichip.org/w/index.php?title=renesas/r-car/m3_(sip)&oldid=71200"
Facts about "R-Car M3 (SiP) - Renesas"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
R-Car M3 (SiP) - Renesas#package +
core count7 +
core nameCortex-A53 +, Cortex-A57 + and Cortex-R7 +
core voltage0.9 V (9 dV, 90 cV, 900 mV) +
designerRenesas + and ARM Holdings +
familyR-Car +
first announcedOctober 19, 2016 +
first launchedOctober 2016 +
full page namerenesas/r-car/m3 (sip) +
has ecc memory supportfalse +
instance ofmicroprocessor +
integrated gpuPowerVR GX6250 +
integrated gpu designerImagination Technologies +
io voltage3.3 V (33 dV, 330 cV, 3,300 mV) +
isaARMv8 +
isa familyARM +
l1$ size480 KiB (491,520 B, 0.469 MiB) +
l1d$ size224 KiB (229,376 B, 0.219 MiB) +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ size1.5 MiB (1,536 KiB, 1,572,864 B, 0.00146 GiB) +
ldateOctober 2016 +
main imageFile:r-car m3 (sip).png +
manufacturerTSMC +
market segmentEmbedded +
max cpu count1 +
max memory bandwidth11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels2 +
microarchitectureCortex-A53 +, Cortex-A57 + and Cortex-R7 +
model numberM3 (SiP) +
nameR-Car M3 (SiP) +
packageFCBGA-1255 +
part numberR8J77960 +
process16 nm (0.016 μm, 1.6e-5 mm) +
series3rd Gen +
smp max ways1 +
supported memory typeLPDDR4-3200 +
technologyCMOS +
thread count7 +
word size64 bit (8 octets, 16 nibbles) +