From WikiChip
Difference between revisions of "intel/xeon e5/e5-2670 v4"
< intel‎ | xeon e5

m (Bot: corrected param)
m (Bot: moving all {{mpu}} to {{chip}})
 
(2 intermediate revisions by the same user not shown)
Line 1: Line 1:
 
{{intel title|Xeon E5-2670 v4}}
 
{{intel title|Xeon E5-2670 v4}}
{{mpu
+
{{chip
 
| name                = Xeon E5-2670 v4
 
| name                = Xeon E5-2670 v4
 
| no image            = Yes
 
| no image            = Yes
Line 126: Line 126:
  
 
== Expansions ==
 
== Expansions ==
{{mpu expansions
+
{{expansions
 
| pcie revision      = 3.0
 
| pcie revision      = 3.0
 
| pcie lanes        = 40
 
| pcie lanes        = 40
Line 135: Line 135:
  
 
== Features ==  
 
== Features ==  
{{mpu features
+
{{x86 features
 
| em64t      = Yes
 
| em64t      = Yes
 
| nx          = Yes
 
| nx          = Yes

Latest revision as of 15:28, 13 December 2017

Edit Values
Xeon E5-2670 v4
General Info
DesignerIntel
ManufacturerIntel
Model NumberE5-2670 v4
S-SpecQK91 (QS)
MarketServer
IntroductionJune 20, 2016 (announced)
June 20, 2016 (launched)
ShopAmazon
General Specs
FamilyXeon E5
SeriesE5-2000
LockedYes
Frequency3,100 MHz
Bus typeQPI
Bus speed4,800 MHz
Bus rate2 × 9.6 GT/s
Clock multiplier31
CPUID406F1
Microarchitecture
MicroarchitectureBroadwell
PlatformGrantley EP 2S
ChipsetC610 Series
Core NameBroadwell EP
Core Family6
Core Model4F
Core SteppingM0
Process14 nm
Transistors4,700,000,000
TechnologyCMOS
Die306.18 mm²
Word Size64 bit
Cores14
Threads28
Max Memory1,536 GiB
Multiprocessing
Max SMP2-Way (Multiprocessor)
Electrical
Vcore1.82 V
VI/O1.2 V ± 3%
TDP120 W
Tcase0 °C – ? °C
Tstorage-25 °C – 125 °C

The Xeon E5-2670 v4 is a 64-bit tetradeca-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for 2S environments. Operating at 3.1 GHz with a turbo boost frequency of ? GHz for a single active core, this MPU has a TDP of 120 W and is manufactured on a 14 nm process (based on Broadwell).


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache[edit]

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 448 KiB
458,752 B
0.438 MiB
14x32 KiB 8-way set associative (per core, write-back)
L1D$ 448 KiB
458,752 B
0.438 MiB
14x32 KiB 8-way set associative (per core, write-back)
L2$ 3.5 MiB
3,584 KiB
3,670,016 B
0.00342 GiB
14x256 KiB 8-way set associative (per core, write-back)
L3$ 35 MiB
35,840 KiB
36,700,160 B
0.0342 GiB
14x2.5 MiB 20-way set associative (shared, per core, write-back)

Graphics[edit]

This microprocessor has no integrated graphics processing unit.

Memory controller[edit]

Integrated Memory Controller
Type DDR4-2400
Controllers 1
Channels 4
ECC Support Yes
Max bandwidth 71.53 GiB/s
Bandwidth (single) 17.88 GiB/s
Bandwidth (dual) 35.76 GiB/s
Max memory 1,536 GiB
Physical Address Extensions 46 bit

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes40
Configsx4, x16


Features[edit]

has advanced vector extensionstrue +
has advanced vector extensions 2true +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel vPro Technology +, Extended Page Tables + and Transactional Synchronization Extensions +
has intel enhanced speedstep technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
l1d$ description8-way set associative +
l1d$ size448 KiB (458,752 B, 0.438 MiB) +
l1i$ description8-way set associative +
l1i$ size448 KiB (458,752 B, 0.438 MiB) +
l2$ description8-way set associative +
l2$ size3.5 MiB (3,584 KiB, 3,670,016 B, 0.00342 GiB) +
l3$ description20-way set associative +
l3$ size35 MiB (35,840 KiB, 36,700,160 B, 0.0342 GiB) +