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    Difference between revisions of "intel/xeon e3/e3-1225 v6"    
                	
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| {{intel title|Xeon E3-1225 v6}} | {{intel title|Xeon E3-1225 v6}} | ||
| − | {{ | + | {{chip | 
| − | + | |name=Xeon E3-1225 v6 | |
| − | | name  | + | |no image=Yes | 
| − | | no image  | + | |designer=Intel | 
| − | + | |manufacturer=Intel | |
| − | + | |model number=E3-1225 v6 | |
| − | + | |part number=CM8067702871024 | |
| − | | designer  | + | |part number 2=BX80677E31225V6 | 
| − | | manufacturer  | + | |s-spec=SR32C | 
| − | | model number  | + | |market=Workstation | 
| − | | part number  | + | |market 2=Server | 
| − | | part number 2  | + | |first announced=March 28, 2017 | 
| − | | market  | + | |first launched=March 28, 2017 | 
| − | | first announced  | + | |release price=$213 | 
| − | | first launched  | + | |family=Xeon E3 | 
| − | |  | + | |series=E3-1200 v6 | 
| − | + | |locked=Yes | |
| − | + | |frequency=3,300 MHz | |
| − | | family  | + | |turbo frequency1=3,700 MHz | 
| − | | series  | + | |bus type=DMI 3.0 | 
| − | | locked  | + | |bus rate=8 GT/s | 
| − | | frequency  | + | |clock multiplier=33 | 
| − | + | |isa=x86-64 | |
| − | | turbo frequency1  | + | |isa family=x86 | 
| − | + | |microarch=Kaby Lake | |
| − | + | |platform=Greenlow | |
| − | + | |chipset=Sunrise Point | |
| − | | bus type  | + | |chipset 2=Union Point | 
| − | + | |core name=Kaby Lake DT | |
| − | | bus rate  | + | |core family=6 | 
| − | | clock multiplier  | + | |core model=158 | 
| − | |  | + | |core stepping=B0 | 
| − | + | |process=14 nm | |
| − | |  | + | |technology=CMOS | 
| − | + | |word size=64 bit | |
| − | + | |core count=4 | |
| − | | microarch  | + | |thread count=4 | 
| − | | platform  | + | |max cpus=1 | 
| − | | chipset  | + | |max memory=64 GiB | 
| − | | core name  | + | |v core min=0.55 V | 
| − | | core family  | + | |v core max=1.52 V | 
| − | | core model  | + | |tdp=73 W | 
| − | | core stepping  | + | |tstorage min=-25 °C | 
| − | | process  | + | |tstorage max=125 °C | 
| − | + | |package module 1={{packages/intel/lga-1151}} | |
| − | | technology  | ||
| − | |||
| − | | word size  | ||
| − | | core count  | ||
| − | | thread count  | ||
| − | | max cpus  | ||
| − | | max memory  | ||
| − | |||
| − | |||
| − | | v core  | ||
| − | | v core  | ||
| − | |||
| − | | tdp  | ||
| − | |  | ||
| − | |  | ||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | | package  | ||
| − | |||
| − | |||
| − | |||
| − | |||
| }} | }} | ||
| − | + | '''Xeon E3-1225 v6''' is a {{arch|64}} [[quad-core]] [[x86]] workstation/entry server microprocessor introduced by [[Intel]] in early [[2017]]. This chip, which is based on the {{intel|Kaby Lake|l=arch}} microarchitecture, is fabricated on Intel's [[14 nm process|14nm+ process]]. The E3-1225 v6 operates at 3.3 GHz with a TDP of 73 W supporting a {{intel|Turbo Boost}} frequency of 3.7 GHz. The processor supports up to 64 GiB of dual-channel DDR4-2400 ECC memory and incorporates Intel's {{intel|HD Graphics P630}} [[IGP]] operating at 350 MHz with a burst frequency of 1.15 GHz. | |
| − | |||
| − | |||
| − | {{ | ||
| == Cache == | == Cache == | ||
| Line 84: | Line 55: | ||
| |l1i break=4x32 KiB | |l1i break=4x32 KiB | ||
| |l1i desc=8-way set associative | |l1i desc=8-way set associative | ||
| − | |||
| |l1d cache=128 KiB | |l1d cache=128 KiB | ||
| |l1d break=4x32 KiB | |l1d break=4x32 KiB | ||
| Line 101: | Line 71: | ||
| == Memory controller == | == Memory controller == | ||
| {{memory controller | {{memory controller | ||
| − | |type=DDR3L- | + | |type=DDR3L-1866 | 
| − | |type 2 | + | |type 2=DDR4-2400 | 
| − | |||
| |ecc=Yes | |ecc=Yes | ||
| |max mem=64 GiB | |max mem=64 GiB | ||
| Line 129: | Line 98: | ||
| | execution units     = 24 | | execution units     = 24 | ||
| | max displays        = 3 | | max displays        = 3 | ||
| − | | max memory          =  | + | | max memory          = 1.7 GiB | 
| − | | frequency           =  | + | | frequency           = 350 MHz | 
| | max frequency       = 1,150 MHz | | max frequency       = 1,150 MHz | ||
| Line 178: | Line 147: | ||
| |x8664=Yes | |x8664=Yes | ||
| |nx=Yes | |nx=Yes | ||
| − | |||
| − | |||
| |mmx=Yes | |mmx=Yes | ||
| |emmx=Yes | |emmx=Yes | ||
| Line 191: | Line 158: | ||
| |avx=Yes | |avx=Yes | ||
| |avx2=Yes | |avx2=Yes | ||
| − | + | ||
| |abm=Yes | |abm=Yes | ||
| |tbm=No | |tbm=No | ||
| Line 211: | Line 178: | ||
| |eist=Yes | |eist=Yes | ||
| |sst=Yes | |sst=Yes | ||
| − | |flex= | + | |flex=No | 
| |fastmem=No | |fastmem=No | ||
| − | |isrt= | + | |isrt=No | 
| |sba=No | |sba=No | ||
| − | |mwt= | + | |mwt=No | 
| − | |sipp= | + | |sipp=No | 
| |att=No | |att=No | ||
| |ipt=No | |ipt=No | ||
| |tsx=Yes | |tsx=Yes | ||
| |txt=Yes | |txt=Yes | ||
| − | |ht= | + | |ht=No | 
| |vpro=Yes | |vpro=Yes | ||
| |vtx=Yes | |vtx=Yes | ||
| Line 230: | Line 197: | ||
| |securekey=Yes | |securekey=Yes | ||
| |osguard=Yes | |osguard=Yes | ||
| + | |3dnow=No | ||
| + | |e3dnow=No | ||
| |smartmp=No | |smartmp=No | ||
| |powernow=No | |powernow=No | ||
| + | |amdvi=No | ||
| |amdv=No | |amdv=No | ||
| |rvi=No | |rvi=No | ||
| + | |smt=No | ||
| + | |sensemi=No | ||
| + | |xfr=No | ||
| + | }} | ||
| + | |||
| + | == Benchmarks == | ||
| + | {{benchmarks main | ||
| + | | | ||
| + | {{benchmark entry|type=spec_cpu2017|test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171030-00234.html|test_timestamp=2017-10-22 08:02:53-0400|chip_count=1|core_count=4|copies_count=4|vendor=Fujitsu|system=PRIMERGY TX1330 M3, Intel Xeon E3-1225 v6, 3.3 GHz|SPECrate2017_int_base=21.7|SPECrate2017_int_peak=}} | ||
| }} | }} | ||
Latest revision as of 16:26, 13 December 2017
| Edit Values | ||||||||||||
| Xeon E3-1225 v6 | ||||||||||||
| General Info | ||||||||||||
| Designer | Intel | |||||||||||
| Manufacturer | Intel | |||||||||||
| Model Number | E3-1225 v6 | |||||||||||
| Part Number | CM8067702871024, BX80677E31225V6 | |||||||||||
| S-Spec | SR32C | |||||||||||
| Market | Workstation, Server | |||||||||||
| Introduction | March 28, 2017 (announced) March 28, 2017 (launched) | |||||||||||
| Release Price | $213 | |||||||||||
| Shop | Amazon | |||||||||||
| General Specs | ||||||||||||
| Family | Xeon E3 | |||||||||||
| Series | E3-1200 v6 | |||||||||||
| Locked | Yes | |||||||||||
| Frequency | 3,300 MHz | |||||||||||
| Turbo Frequency | 3,700 MHz (1 core) | |||||||||||
| Bus type | DMI 3.0 | |||||||||||
| Bus rate | 8 GT/s | |||||||||||
| Clock multiplier | 33 | |||||||||||
| Microarchitecture | ||||||||||||
| ISA | x86-64 (x86) | |||||||||||
| Microarchitecture | Kaby Lake | |||||||||||
| Platform | Greenlow | |||||||||||
| Chipset | Sunrise Point, Union Point | |||||||||||
| Core Name | Kaby Lake DT | |||||||||||
| Core Family | 6 | |||||||||||
| Core Model | 158 | |||||||||||
| Core Stepping | B0 | |||||||||||
| Process | 14 nm | |||||||||||
| Technology | CMOS | |||||||||||
| Word Size | 64 bit | |||||||||||
| Cores | 4 | |||||||||||
| Threads | 4 | |||||||||||
| Max Memory | 64 GiB | |||||||||||
| Multiprocessing | ||||||||||||
| Max SMP | 1-Way (Uniprocessor) | |||||||||||
| Electrical | ||||||||||||
| Vcore | 0.55 V-1.52 V | |||||||||||
| TDP | 73 W | |||||||||||
| Tstorage | -25 °C – 125 °C | |||||||||||
| Packaging | ||||||||||||
| 
 | ||||||||||||
Xeon E3-1225 v6 is a 64-bit quad-core x86 workstation/entry server microprocessor introduced by Intel in early 2017. This chip, which is based on the Kaby Lake microarchitecture, is fabricated on Intel's 14nm+ process. The E3-1225 v6 operates at 3.3 GHz with a TDP of 73 W supporting a Turbo Boost frequency of 3.7 GHz. The processor supports up to 64 GiB of dual-channel DDR4-2400 ECC memory and incorporates Intel's HD Graphics P630 IGP operating at 350 MHz with a burst frequency of 1.15 GHz.
Cache[edit]
- Main article: Kaby Lake § Cache
|  | Cache Organization  Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. | ||||||||||||||||||||||||||||||||||||
| 
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Memory controller[edit]
|  | Integrated Memory Controller | |||||||||||||
| 
 | ||||||||||||||
Expansions[edit]
|  | Expansion Options | |||||||
| 
 | ||||||||
Graphics[edit]
|  | Integrated Graphics Information | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 
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| [Edit] Kaby Lake (Gen9.5) Hardware Accelerated Video Capabilities | |||||||
|---|---|---|---|---|---|---|---|
| Codec | Encode | Decode | |||||
| Profiles | Levels | Max Resolution | Profiles | Levels | Max Resolution | ||
| MPEG-2 (H.262) | Main | High | 1080p (FHD) | Main | Main, High | 1080p (FHD) | |
| MPEG-4 AVC (H.264) | High, Main | 5.1 | 2160p (4K) | Main, High, MVC, Stereo | 5.1 | 2160p (4K) | |
| JPEG/MJPEG | Baseline | - | 16k x 16k | Baseline | Unified | 16k x 16k | |
| HEVC (H.265) | Main, Main 10 | 5.1 | 2160p (4K) | Main, Main 10 | 5.1 | 2160p (4K) | |
| VC-1 | ✘ | Advanced, Main, Simple | 3, High, Simple | 3840x3840 | |||
| VP8 | Unified | Unified | N/A | 0 | Unified | 1080p | |
| VP9 | 0 | 2160p (4K) | 0, 2 | Unified | 2160p (4K) | ||
Features[edit]
[Edit/Modify Supported Features]
Benchmarks[edit]
Test: SPEC CPU2017
Tested: 2017-10-22 08:02:53-0400
Chips: 1, Cores: 4, Copies: 4 Vendor: Fujitsu
 Vendor: Fujitsu
System: PRIMERGY TX1330 M3, Intel Xeon E3-1225 v6, 3.3 GHz
Tested: 2017-10-22 08:02:53-0400
Chips: 1, Cores: 4, Copies: 4

System: PRIMERGY TX1330 M3, Intel Xeon E3-1225 v6, 3.3 GHz
SPECrate2017_int_base: 21.7
Facts about "Xeon E3-1225 v6  - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon E3-1225 v6 - Intel#io + | 
| device id | 0x591D + | 
| has advanced vector extensions | true + | 
| has advanced vector extensions 2 | true + | 
| has ecc memory support | true + | 
| has extended page tables support | true + | 
| has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions +, Software Guard Extensions +, Secure Key Technology +, OS Guard +, Flex Memory Access +, Smart Response Technology +, My WiFi Technology + and Stable Image Platform Program + | 
| has intel enhanced speedstep technology | true + | 
| has intel flex memory access support | true + | 
| has intel my wifi technology support | true + | 
| has intel secure key technology | true + | 
| has intel smart response technology support | true + | 
| has intel speed shift technology | true + | 
| has intel stable image platform program support | true + | 
| has intel supervisor mode execution protection | true + | 
| has intel trusted execution technology | true + | 
| has intel turbo boost technology 2 0 | true + | 
| has intel vpro technology | true + | 
| has intel vt-d technology | true + | 
| has intel vt-x technology | true + | 
| has second level address translation support | true + | 
| has simultaneous multithreading | true + | 
| has transactional synchronization extensions | true + | 
| has x86 advanced encryption standard instruction set extension | true + | 
| integrated gpu | HD Graphics P630 + | 
| integrated gpu base frequency | 400 MHz (0.4 GHz, 400,000 KHz) + | 
| integrated gpu designer | Intel + | 
| integrated gpu execution units | 24 + | 
| integrated gpu max frequency | 1,150 MHz (1.15 GHz, 1,150,000 KHz) + | 
| integrated gpu max memory | 65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB) + | 
| l1$ size | 256 KiB (262,144 B, 0.25 MiB) + | 
| l1d$ description | 8-way set associative + | 
| l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + | 
| l1i$ description | 8-way set associative + | 
| l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + | 
| l2$ description | 4-way set associative + | 
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + | 
| l3$ description | 16-way set associative + | 
| l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + | 
| max memory bandwidth | 35.76 GiB/s (36,618.24 MiB/s, 38.397 GB/s, 38,397.008 MB/s, 0.0349 TiB/s, 0.0384 TB/s) + | 
| max memory channels | 2 + | 
| max pcie lanes | 16 + | 
| supported memory type | DDR3L-1600 +, LPDDR3-2133 + and DDR4-2400 + | 
| x86/has memory protection extensions | true + | 
| x86/has software guard extensions | true + | 

