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Difference between revisions of "intel/core m/5y51"
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{{title|Core M 5Y51}} | {{title|Core M 5Y51}} | ||
− | {{ | + | {{chip |
| name = Core M 5Y51 | | name = Core M 5Y51 | ||
| no image = Yes | | no image = Yes | ||
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| cpuid = | | cpuid = | ||
+ | | isa family = x86 | ||
+ | | isa = x86-64 | ||
| microarch = Broadwell | | microarch = Broadwell | ||
| platform = | | platform = | ||
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| thread count = 4 | | thread count = 4 | ||
| max cpus = 1 | | max cpus = 1 | ||
− | | max memory = 16 | + | | max memory = 16 GiB |
+ | |||
− | |||
| v core = | | v core = | ||
| v core tolerance = | | v core tolerance = | ||
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{{main|intel/microarchitectures/broadwell#Memory_Hierarchy|l1=Broadwell § Cache}} | {{main|intel/microarchitectures/broadwell#Memory_Hierarchy|l1=Broadwell § Cache}} | ||
{{cache info | {{cache info | ||
− | |l1i cache=64 | + | |l1i cache=64 KiB |
− | |l1i break=2x32 | + | |l1i break=2x32 KiB |
|l1i desc=8-way set associative | |l1i desc=8-way set associative | ||
|l1i extra=(per core) | |l1i extra=(per core) | ||
− | |l1d cache=64 | + | |l1d cache=64 KiB |
− | |l1d break=2x32 | + | |l1d break=2x32 KiB |
|l1d desc=8-way set associative | |l1d desc=8-way set associative | ||
|l1d extra=(per core) | |l1d extra=(per core) | ||
− | |l2 cache=512 | + | |l2 cache=512 MiB |
− | |l2 break=2x256 | + | |l2 break=2x256 KiB |
|l2 desc=8-way set associative | |l2 desc=8-way set associative | ||
|l2 extra=(per core) | |l2 extra=(per core) | ||
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| frequency = 300 MHz | | frequency = 300 MHz | ||
| max frequency = 900 MHz | | max frequency = 900 MHz | ||
− | | max memory = 16 | + | | max memory = 16 GiB |
| output crt = | | output crt = | ||
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== Expansions == | == Expansions == | ||
− | {{ | + | {{expansions |
| pcie revision = 2.0 | | pcie revision = 2.0 | ||
| pcie lanes = 12 | | pcie lanes = 12 | ||
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== Features == | == Features == | ||
− | {{ | + | {{x86 features |
| em64t = Yes | | em64t = Yes | ||
| nx = Yes | | nx = Yes |
Latest revision as of 16:24, 13 December 2017
Edit Values | |
Core M 5Y51 | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | 5Y51 |
Part Number | FH8065802061802 |
S-Spec | SR23L |
Market | Mobile |
Introduction | November, 2014 (announced) January, 2015 (launched) |
Shop | Amazon |
General Specs | |
Family | Core M |
Series | 5000 |
Locked | Yes |
Frequency | 1100 MHz |
Turbo Frequency | Yes |
Turbo Frequency | 2600 MHz (1 core) |
Bus type | DMI 2.0 |
Clock multiplier | 11 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Broadwell |
Core Name | Broadwell Y |
Core Family | 06 |
Core Model | 3D |
Core Stepping | F0 |
Process | 14 nm |
Transistors | 1,300,000,000 |
Technology | CMOS |
Die | 82 mm² |
Word Size | 64 bit |
Cores | 2 |
Threads | 4 |
Max Memory | 16 GiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
SDP | 3.5 W |
TDP | 4.5 W |
cTDP down | 3.5 W |
cTDP down frequency | 600 MHz |
cTDP up | 6 W |
cTDP up frequency | 1.3 GHz |
OP Temperature | 0 °C – 95 °C |
The Core M 5Y51 is an ultra-low power dual-core 64-bit x86 microprocessor introduced by Intel in 2015. This MPU operates at 1.1 GHz with a max turbo frequency of 2.6 GHz. The 5Y51 has a configurable TDP-down of 3.5 W @ 600 MHz and a configurable TDP-up of 6 W @ 1.3 GHz. This chip, which is manufactured in 14 nm process based on the Broadwell microarchitecture and incorporates Intel's HD Graphics 5300 Gen8 GPU clocked at 300 MHz with turbo frequency of 900 MHz.
Cache[edit]
- Main article: Broadwell § Cache
Cache Info [Edit Values] | ||
L1I$ | 64 KiB 65,536 B 0.0625 MiB |
2x32 KiB 8-way set associative (per core) |
L1D$ | 64 KiB 65,536 B 0.0625 MiB |
2x32 KiB 8-way set associative (per core) |
L2$ | 512 MiB 524,288 KiB 536,870,912 B 0.5 GiB |
2x256 KiB 8-way set associative (per core) |
L3$ | 4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB |
2x2 MiB (shared LLC) |
Graphics[edit]
Integrated Graphic Information | |
GPU | Intel HD Graphics 5300 |
Device ID | 0x161E |
Execution Units | 24 |
Displays | 3 |
Frequency | 300 MHz 0.3 GHz
300,000 KHz |
Max frequency | 900 MHz 0.9 GHz
900,000 KHz |
Max memory | 16 GiB 16,384 MiB
16,777,216 KiB 17,179,869,184 B |
Output | DisplayPort, Embedded DisplayPort, HDMI |
DirectX | 11.2 |
OpenGL | 4.3 |
OpenCL | 2.0 |
HDMI | 1.4a |
DP | 1.2 |
eDP | 1.3 |
Max HDMI Res | 2560x1600 @60 Hz, 4096x2304 @24 Hz |
Max DVI Res | 1920x1200 @60 Hz |
Max DP Res | 2560x1600 @60 Hz, 3840x2160 @60 Hz |
Max eDP Res | 2560x1600 @60 Hz, 3840x2160 @60 Hz |
Intel Quick Sync Video | |
Intel InTru 3D | |
Intel Insider | |
Intel WiDi (Wireless Display) | |
Intel Flexible Display Interface (FDI) | |
Intel Clear Video |
- AVC/H.264 Encode
- MPEG2 Encode
- MVC HW Encode
- JPEG/MJPEG Hardware Encode
- Blu-ray* Disc Playback
- AVC/H.264, MPEG2, VC1 Decode
Memory controller[edit]
Integrated Memory Controller | |
Type | LPDDR3-1333, LPDDR3-1600, DDR3L-1600, DDR3L-RS1600 |
Controllers | 1 |
Channels | 2 |
ECC Support | No |
Max bandwidth | 25.6 GB/s |
Max memory | 16 GB |
Expansions[edit]
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Expansion Options
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Features[edit]
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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Drivers[edit]
Facts about "Core M 5Y51"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Core M 5Y51#io + |
base frequency | 1,100 MHz (1.1 GHz, 1,100,000 kHz) + |
bus type | DMI 2.0 + |
clock multiplier | 11 + |
core count | 2 + |
core family | 06 + |
core model | 3D + |
core name | Broadwell Y + |
core stepping | F0 + |
designer | Intel + |
device id | 0x161E + |
die area | 82 mm² (0.127 in², 0.82 cm², 82,000,000 µm²) + |
drivers url | https://downloadcenter.intel.com/product/94028 + |
family | Core M + |
first announced | November 2014 + |
first launched | January 2015 + |
full page name | intel/core m/5y51 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has extended page tables support | true + |
has feature | integrated gpu +, Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology + and Extended Page Tables + |
has intel enhanced speedstep technology | true + |
has intel turbo boost technology 2 0 | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
integrated gpu | Intel HD Graphics 5300 + |
integrated gpu base frequency | 300 MHz (0.3 GHz, 300,000 KHz) + |
integrated gpu max frequency | 900 MHz (0.9 GHz, 900,000 KHz) + |
integrated gpu max memory | 16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB) + |
isa | x86-64 + |
isa family | x86 + |
l1d$ description | 8-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 512 MiB (524,288 KiB, 536,870,912 B, 0.5 GiB) + |
l3$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
ldate | January 2015 + |
manufacturer | Intel + |
market segment | Mobile + |
max cpu count | 1 + |
max memory | 16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB, 0.0156 TiB) + |
max operating temperature | 95 °C + |
max pcie lanes | 12 + |
microarchitecture | Broadwell + |
min operating temperature | 0 °C + |
model number | 5Y51 + |
name | Core M 5Y51 + |
part number | FH8065802061802 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
s-spec | SR23L + |
sdp | 3.5 W (3,500 mW, 0.00469 hp, 0.0035 kW) + |
series | 5000 + |
smp max ways | 1 + |
tdp | 4.5 W (4,500 mW, 0.00603 hp, 0.0045 kW) + |
tdp down | 3.5 W (3,500 mW, 0.00469 hp, 0.0035 kW) + |
tdp down frequency | 600 MHz (0.6 GHz, 600,000 kHz) + |
tdp up | 6 W (6,000 mW, 0.00805 hp, 0.006 kW) + |
tdp up frequency | 1,300 MHz (1.3 GHz, 1,300,000 kHz) + |
technology | CMOS + |
thread count | 4 + |
transistor count | 1,300,000,000 + |
turbo frequency (1 core) | 2,600 MHz (2.6 GHz, 2,600,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |