From WikiChip
Difference between revisions of "intel/core i5/i5-9400"
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Revision as of 15:21, 13 December 2017
| Edit Values | |
| Core i5-9400 | |
| General Info | |
| Designer | Intel |
| Manufacturer | Intel |
| Model Number | i5-9400 |
| Market | Desktop |
| Shop | Amazon |
| General Specs | |
| Family | Core i5 |
| Series | i5-9000 |
| Locked | Yes |
| Microarchitecture | |
| ISA | x86-64 (x86) |
| Microarchitecture | Ice Lake |
| Core Name | Ice Lake S |
| Process | 10 nm |
| Technology | CMOS |
| Word Size | 64 bit |
| Cores | 6 |
| Threads | 12 |
| Max Memory | 64 GiB |
| Multiprocessing | |
| Max SMP | 1-Way (Uniprocessor) |
| Electrical | |
| TDP | 65 W |
Core i5-9400 is a planned 64-bit mid-range performance x86 desktop processor by Intel set to be introduced in 2018/2019. The i5-9400 is fabricated on Intel's 2nd generation 10nm+ process based on the Ice Lake microarchitecture.
Cache
- Main article: Ice Lake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Facts about "Core i5-9400 - Intel"
| l1$ size | 512 KiB (524,288 B, 0.5 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l2$ description | 4-way set associative + |
| l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
| l3$ description | 16-way set associative + |
| l3$ size | 12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) + |