From WikiChip
Difference between revisions of "intel/core i5/i5-2557m"
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{{intel title|Core i5-2557M}} | {{intel title|Core i5-2557M}} | ||
− | {{ | + | {{chip |
|name=Core i5-2557M | |name=Core i5-2557M | ||
|no image=Yes | |no image=Yes | ||
Line 9: | Line 9: | ||
|s-spec=SR0CS | |s-spec=SR0CS | ||
|market=Mobile | |market=Mobile | ||
+ | |first announced=June, 2011 | ||
+ | |first launched=June, 2011 | ||
+ | |release price=$250 | ||
|family=Core i5 | |family=Core i5 | ||
|series=i5-2000 | |series=i5-2000 | ||
Line 48: | Line 51: | ||
|package module 1={{packages/intel/fcbga-1023}} | |package module 1={{packages/intel/fcbga-1023}} | ||
}} | }} | ||
+ | '''Core i5-2557M''' is a [[dual-core]] mid-range performance mobile [[x86]] microprocessor introduced by [[Intel]] in mid-[[2011]]. This chip, which is fabricated on a [[32 nm process]] based on the {{intel|Sandy Bridge|l=arch}} microarchitecture, operates at 1.7 GHz with a [[TDP]] of 17 Watts and a {{intel|Turbo Boost}} frequency of up to 2.7 GHz. The i5-2557M incorporates {{intel|HD Graphics 3000}} integrated graphics operating at 350 MHz with a burst frequency of 1.2 GHz and supports up to 16 GiB of dual-channel DDR3-1333 memory. | ||
== Cache == | == Cache == | ||
+ | {{main|intel/microarchitectures/sandy_bridge#Memory_Hierarchy|l1=Sandy Bridge § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=128 KiB | ||
+ | |l1i cache=64 KiB | ||
+ | |l1i break=2x32 KiB | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1d cache=64 KiB | ||
+ | |l1d break=2x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d policy=write-back | ||
+ | |l2 cache=512 KiB | ||
+ | |l2 break=2x256 KiB | ||
+ | |l2 desc=8-way set associative | ||
+ | |l2 policy=write-back | ||
+ | |l3 cache=3 MiB | ||
+ | |l3 break=2x1.5 MiB | ||
+ | |l3 desc=12-way set associative | ||
+ | |l3 policy=write-back | ||
+ | }} | ||
== Memory controller == | == Memory controller == | ||
Line 75: | Line 98: | ||
|pcie config 3=1x8+2x4 | |pcie config 3=1x8+2x4 | ||
}} | }} | ||
+ | }} | ||
+ | |||
+ | == Wireless == | ||
+ | {{wireless links | ||
+ | |4g=yes | ||
+ | |wimax=yes | ||
}} | }} | ||
Line 112: | Line 141: | ||
== Features == | == Features == | ||
− | {{x86 features}} | + | {{x86 features |
+ | |real=Yes | ||
+ | |protected=Yes | ||
+ | |smm=Yes | ||
+ | |fpu=Yes | ||
+ | |x8616=Yes | ||
+ | |x8632=Yes | ||
+ | |x8664=Yes | ||
+ | |nx=Yes | ||
+ | |mmx=Yes | ||
+ | |emmx=Yes | ||
+ | |sse=Yes | ||
+ | |sse2=Yes | ||
+ | |sse3=Yes | ||
+ | |ssse3=Yes | ||
+ | |sse41=Yes | ||
+ | |sse42=Yes | ||
+ | |sse4a=No | ||
+ | |avx=Yes | ||
+ | |avx2=No | ||
+ | |avx512f=No | ||
+ | |avx512cd=No | ||
+ | |avx512er=No | ||
+ | |avx512pf=No | ||
+ | |avx512bw=No | ||
+ | |avx512dq=No | ||
+ | |avx512vl=No | ||
+ | |avx512ifma=No | ||
+ | |avx512vbmi=No | ||
+ | |avx5124fmaps=No | ||
+ | |avx5124vnniw=No | ||
+ | |avx512vpopcntdq=No | ||
+ | |abm=No | ||
+ | |tbm=No | ||
+ | |bmi1=No | ||
+ | |bmi2=No | ||
+ | |fma3=No | ||
+ | |fma4=No | ||
+ | |aes=Yes | ||
+ | |rdrand=No | ||
+ | |sha=No | ||
+ | |xop=No | ||
+ | |adx=No | ||
+ | |clmul=Yes | ||
+ | |f16c=No | ||
+ | |tbt1=No | ||
+ | |tbt2=No | ||
+ | |tbmt3=No | ||
+ | |bpt=No | ||
+ | |eist=Yes | ||
+ | |sst=No | ||
+ | |flex=Yes | ||
+ | |fastmem=Yes | ||
+ | |ivmd=No | ||
+ | |intelnodecontroller=No | ||
+ | |intelnode=No | ||
+ | |kpt=No | ||
+ | |ptt=No | ||
+ | |intelrunsure=No | ||
+ | |mbe=No | ||
+ | |isrt=No | ||
+ | |sba=No | ||
+ | |mwt=Yes | ||
+ | |sipp=No | ||
+ | |att=Yes | ||
+ | |ipt=Yes | ||
+ | |tsx=No | ||
+ | |txt=Yes | ||
+ | |ht=Yes | ||
+ | |vpro=Yes | ||
+ | |vtx=Yes | ||
+ | |vtd=Yes | ||
+ | |ept=Yes | ||
+ | |mpx=No | ||
+ | |sgx=No | ||
+ | |securekey=No | ||
+ | |osguard=No | ||
+ | |intqat=No | ||
+ | |3dnow=No | ||
+ | |e3dnow=No | ||
+ | |smartmp=No | ||
+ | |powernow=No | ||
+ | |amdvi=No | ||
+ | |amdv=No | ||
+ | |amdsme=No | ||
+ | |amdtsme=No | ||
+ | |amdsev=No | ||
+ | |rvi=No | ||
+ | |smt=No | ||
+ | |sensemi=No | ||
+ | |xfr=No | ||
+ | }} |
Latest revision as of 15:19, 13 December 2017
Edit Values | |||||||||
Core i5-2557M | |||||||||
General Info | |||||||||
Designer | Intel | ||||||||
Manufacturer | Intel | ||||||||
Model Number | i5-2557M | ||||||||
Part Number | AV8062701047204 | ||||||||
S-Spec | SR0CS | ||||||||
Market | Mobile | ||||||||
Introduction | June, 2011 (announced) June, 2011 (launched) | ||||||||
Release Price | $250 | ||||||||
Shop | Amazon | ||||||||
General Specs | |||||||||
Family | Core i5 | ||||||||
Series | i5-2000 | ||||||||
Locked | Yes | ||||||||
Frequency | 1,700 MHz | ||||||||
Turbo Frequency | 2,700 MHz (1 core), 2,400 MHz (2 cores) | ||||||||
Bus type | DMI 2.0 | ||||||||
Bus rate | 4 × 5 GT/s | ||||||||
Clock multiplier | 17 | ||||||||
CPUID | 0x206A7 | ||||||||
Microarchitecture | |||||||||
ISA | x86-64 (x86) | ||||||||
Microarchitecture | Sandy Bridge | ||||||||
Platform | Sandy Bridge M | ||||||||
Chipset | Cougar Point | ||||||||
Core Name | Sandy Bridge M | ||||||||
Core Family | 6 | ||||||||
Core Model | 42 | ||||||||
Core Stepping | J1 | ||||||||
Process | 32 nm | ||||||||
Transistors | 624,000,000 | ||||||||
Technology | CMOS | ||||||||
Die | 149 mm² | ||||||||
Word Size | 64 bit | ||||||||
Cores | 2 | ||||||||
Threads | 4 | ||||||||
Max Memory | 8 GiB | ||||||||
Multiprocessing | |||||||||
Max SMP | 1-Way (Uniprocessor) | ||||||||
Electrical | |||||||||
Power (idle) | 2.3 W | ||||||||
Vcore | 0.3 V-1.52 V | ||||||||
TDP | 17 W | ||||||||
Tjunction | 0 °C – 100 °C | ||||||||
Tstorage | -25 °C – 125 °C | ||||||||
Packaging | |||||||||
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Core i5-2557M is a dual-core mid-range performance mobile x86 microprocessor introduced by Intel in mid-2011. This chip, which is fabricated on a 32 nm process based on the Sandy Bridge microarchitecture, operates at 1.7 GHz with a TDP of 17 Watts and a Turbo Boost frequency of up to 2.7 GHz. The i5-2557M incorporates HD Graphics 3000 integrated graphics operating at 350 MHz with a burst frequency of 1.2 GHz and supports up to 16 GiB of dual-channel DDR3-1333 memory.
Cache[edit]
- Main article: Sandy Bridge § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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Expansions[edit]
Expansion Options |
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Wireless[edit]
Wireless Communications | ||||
Cellular | ||||
4G |
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Graphics[edit]
Integrated Graphics Information
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[Edit] Sandy Bridge (Gen6) Hardware Accelerated Video Capabilities | |||||||
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Codec | Encode | Decode | |||||
Profiles | Levels | Max Resolution | Profiles | Levels | Max Resolution | ||
MPEG-2 (H.262) | ✘ | Main | Main, High | Up to 80 Mbps | |||
MPEG-4 AVC (H.264) | Main | 4.1 | Up to 40 Mbps | Main, High | 4.1 | Up to 40 Mbps | |
VC-1 | ✘ | Advanced, Main, Simple | 3, High, Simple | Up to 40 Mbps |
Features[edit]
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
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Facts about "Core i5-2557M - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Core i5-2557M - Intel#package + and Core i5-2557M - Intel#pcie + |
base frequency | 1,700 MHz (1.7 GHz, 1,700,000 kHz) + |
bus links | 4 + |
bus rate | 5,000 MT/s (5 GT/s, 5,000,000 kT/s) + |
bus type | DMI 2.0 + |
chipset | Cougar Point + |
clock multiplier | 17 + |
core count | 2 + |
core family | 6 + |
core model | 42 + |
core name | Sandy Bridge M + |
core stepping | J1 + |
core voltage (max) | 1.52 V (15.2 dV, 152 cV, 1,520 mV) + |
core voltage (min) | 0.3 V (3 dV, 30 cV, 300 mV) + |
cpuid | 0x206A7 + |
designer | Intel + |
device id | 0x116 + |
die area | 149 mm² (0.231 in², 1.49 cm², 149,000,000 µm²) + |
family | Core i5 + |
first announced | June 2011 + |
first launched | June 2011 + |
full page name | intel/core i5/i5-2557m + |
has 4g support | true + |
has advanced vector extensions | true + |
has ecc memory support | false + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Flex Memory Access +, My WiFi Technology + and Identity Protection Technology + |
has intel enhanced speedstep technology | true + |
has intel flex memory access support | true + |
has intel identity protection technology support | true + |
has intel my wifi technology support | true + |
has intel trusted execution technology | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has wimax support | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
integrated gpu | HD Graphics 3000 + |
integrated gpu base frequency | 350 MHz (0.35 GHz, 350,000 KHz) + |
integrated gpu designer | Intel + |
integrated gpu execution units | 12 + |
integrated gpu max frequency | 1,200 MHz (1.2 GHz, 1,200,000 KHz) + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
l3$ description | 12-way set associative + |
l3$ size | 3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) + |
ldate | June 2011 + |
manufacturer | Intel + |
market segment | Mobile + |
max cpu count | 1 + |
max junction temperature | 373.15 K (100 °C, 212 °F, 671.67 °R) + |
max memory | 8,192 MiB (8,388,608 KiB, 8,589,934,592 B, 8 GiB, 0.00781 TiB) + |
max memory bandwidth | 19.87 GiB/s (20,346.88 MiB/s, 21.335 GB/s, 21,335.25 MB/s, 0.0194 TiB/s, 0.0213 TB/s) + |
max memory channels | 2 + |
max storage temperature | 398.15 K (125 °C, 257 °F, 716.67 °R) + |
microarchitecture | Sandy Bridge + |
min junction temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
min storage temperature | 248.15 K (-25 °C, -13 °F, 446.67 °R) + |
model number | i5-2557M + |
name | Core i5-2557M + |
package | FCBGA-1023 + |
part number | AV8062701047204 + |
platform | Sandy Bridge M + |
power dissipation (idle) | 2.3 W (2,300 mW, 0.00308 hp, 0.0023 kW) + |
process | 32 nm (0.032 μm, 3.2e-5 mm) + |
release price | $ 250.00 (€ 225.00, £ 202.50, ¥ 25,832.50) + |
s-spec | SR0CS + |
series | i5-2000 + |
smp max ways | 1 + |
supported memory type | DDR3-1333 + and DDR3-1066 + |
tdp | 17 W (17,000 mW, 0.0228 hp, 0.017 kW) + |
technology | CMOS + |
thread count | 4 + |
transistor count | 624,000,000 + |
turbo frequency (1 core) | 2,700 MHz (2.7 GHz, 2,700,000 kHz) + |
turbo frequency (2 cores) | 2,400 MHz (2.4 GHz, 2,400,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |