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Difference between revisions of "intel/80486/486dx2-40"
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{{intel title|i486DX2-40}} | {{intel title|i486DX2-40}} | ||
| − | {{ | + | {{chip |
| name = Intel i486DX2-40 | | name = Intel i486DX2-40 | ||
| no image = Yes | | no image = Yes | ||
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| bus rate = 20 MT/s | | bus rate = 20 MT/s | ||
| clock multiplier = 2 | | clock multiplier = 2 | ||
| − | | s-spec = | + | | s-spec = SX722 |
| s-spec es = | | s-spec es = | ||
| s-spec qs = | | s-spec qs = | ||
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| core count = 1 | | core count = 1 | ||
| max cpus = 1 | | max cpus = 1 | ||
| − | | max memory = 4 | + | | max memory = 4 GiB |
| + | |||
| − | |||
| power = | | power = | ||
| v core = 5 V | | v core = 5 V | ||
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{{main|intel/microarchitectures/80486#Memory_Hierarchy|l1=80486 § Cache}} | {{main|intel/microarchitectures/80486#Memory_Hierarchy|l1=80486 § Cache}} | ||
{{cache info | {{cache info | ||
| − | |l1 cache=8 | + | |l1 cache=8 KiB |
| − | |l1 break=1x8 | + | |l1 break=1x8 KiB |
|l1 desc=4-way set associative | |l1 desc=4-way set associative | ||
| − | |l1 extra=(unified, write-through policy ) | + | |l1 extra=(unified, write-through policy) |
}} | }} | ||
Latest revision as of 15:13, 13 December 2017
| Edit Values | |
| Intel i486DX2-40 | |
| General Info | |
| Designer | Intel |
| Manufacturer | Intel |
| Model Number | i486DX2-40 |
| Part Number | A80486DX2-40, SB80486DX2-40 |
| S-Spec | SX722 |
| Introduction | March 3, 1992 (launched) |
| Shop | Amazon |
| General Specs | |
| Family | 80486 |
| Series | 486DX2 |
| Frequency | 40 MHz |
| Bus type | FSB |
| Bus speed | 20 MHz |
| Bus rate | 20 MT/s |
| Clock multiplier | 2 |
| Microarchitecture | |
| Microarchitecture | 80486 |
| Core Name | 486DX2 |
| Process | 1 µm, 800 nm |
| Technology | CMOS |
| Word Size | 32 bit |
| Cores | 1 |
| Max Memory | 4 GiB |
| Multiprocessing | |
| Max SMP | 1-Way (Uniprocessor) |
| Electrical | |
| Vcore | 5 V |
| OP Temperature | 0 °C – 85 °C |
i486DX2-40 was a fourth-generation x86 microprocessor introduced by Intel in 1992. This chip, which is based on the 80486 microarchitecture, had a clock doubler operating at 40 MHz, twice the bus frequency. Like the original i486DX, this chip implemented the 80387 FPU on-die and incorporated System Management Mode (SMM).
Contents
Cache[edit]
- Main article: 80486 § Cache
| Cache Info [Edit Values] | ||
| L1$ | 8 KiB 8,192 B 0.00781 MiB |
1x8 KiB 4-way set associative (unified, write-through policy) |
Graphics[edit]
This chip had no integrated graphics processing unit.
Features[edit]
- System Management Mode (SMM)