Semiconductor & Computer Engineering
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Difference between revisions of "exponential technology/x704/500"
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{{expotech title|X704-500}} | {{expotech title|X704-500}} | ||
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| name = X704-500 | | name = X704-500 | ||
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| power = 85 W | | power = 85 W | ||
| v core = 3.6 V | | v core = 3.6 V | ||
Latest revision as of 15:13, 13 December 2017
| Edit Values | |
| X704-500 | |
| General Info | |
| Designer | Exponential Technology |
| Manufacturer | Hitachi |
| Model Number | X704-500 |
| Market | Desktop |
| Introduction | January 7, 1997 (announced) |
| General Specs | |
| Family | X704 |
| Frequency | 500 MHz |
| Bus type | 60x bus |
| Bus speed | 100 MHz |
| Clock multiplier | 5 |
| Microarchitecture | |
| Microarchitecture | X704 |
| Platform | CHRP |
| Process | 500 nm |
| Transistors | 2,700,000 |
| Technology | BiCMOS |
| Die | 150 mm² |
| Word Size | 32 bit |
| Cores | 1 |
| Threads | 1 |
| Multiprocessing | |
| Max SMP | 1-Way (Uniprocessor) |
| Electrical | |
| Power dissipation | 85 W |
| Vcore | 3.6 V |
X704 500 MHz was a PowerPC-compatible microprocessor operating at 500 MHz announced in January 1997 by Exponential Technology. The company folded before the model ever reaching market (See X704 § History).
Cache[edit]
- Main article: X704 § Cache
Level 3 can be provided externally with cache size of 512 KiB to 2 MiB.
| Cache Info [Edit Values] | ||
| L1I$ | 2 KiB 2,048 B 0.00195 MiB |
1x2 KiB direct mapped |
| L1D$ | 2 KiB 2,048 B 0.00195 MiB |
1x2 KiB direct mapped |
| L2$ | 32 KiB 0.0313 MiB 32,768 B 3.051758e-5 GiB |
1x32 KiB 8-way set associative |
Graphics[edit]
This SoC has no integrated graphics processing unit.
Features[edit]
- Fully PowerPC 60x-compatible architecture
- IEEE 1149.1-compliant JTAG test access port
- IEEE 754-compliant single-precision and double-precision arithmetic
- Support for standard PowerPC 60X bus with 64 bits of data and 32 bits of address
- Support for all PowerPC cache operations
- Support for PowerEndian and BigEndian modes
Documents[edit]
Manuals[edit]
- X704 Technical Summary, 1996
See also[edit]
Facts about "X704-500 - Exponential Technology"
| base frequency | 500 MHz (0.5 GHz, 500,000 kHz) + |
| bus speed | 100 MHz (0.1 GHz, 100,000 kHz) + |
| bus type | 60x bus + |
| clock multiplier | 5 + |
| core count | 1 + |
| core voltage | 3.6 V (36 dV, 360 cV, 3,600 mV) + |
| designer | Exponential Technology + |
| die area | 150 mm² (0.233 in², 1.5 cm², 150,000,000 µm²) + |
| family | X704 + |
| first announced | January 7, 1997 + |
| full page name | exponential technology/x704/500 + |
| instance of | microprocessor + |
| l1d$ description | direct mapped + |
| l1d$ size | 2 KiB (2,048 B, 0.00195 MiB) + |
| l1i$ description | direct mapped + |
| l1i$ size | 2 KiB (2,048 B, 0.00195 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 0.0313 MiB (32 KiB, 32,768 B, 3.051758e-5 GiB) + |
| ldate | January 7, 1997 + |
| manufacturer | Hitachi + |
| market segment | Desktop + |
| max cpu count | 1 + |
| microarchitecture | X704 + |
| model number | X704-500 + |
| name | X704-500 + |
| platform | CHRP + |
| power dissipation | 85 W (85,000 mW, 0.114 hp, 0.085 kW) + |
| process | 500 nm (0.5 μm, 5.0e-4 mm) + |
| smp max ways | 1 + |
| technology | BiCMOS + |
| thread count | 1 + |
| transistor count | 2,700,000 + |
| word size | 32 bit (4 octets, 8 nibbles) + |