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Difference between revisions of "cavium/octeon/cn3860-500bg1521-exp"
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{{cavium title|CN3860-500 EXP}} | {{cavium title|CN3860-500 EXP}} | ||
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| name = Cavium CN3860-500 EXP | | name = Cavium CN3860-500 EXP | ||
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| model number = CN3860-500 EXP | | model number = CN3860-500 EXP | ||
| part number = CN3860-500BG1521-EXP | | part number = CN3860-500BG1521-EXP | ||
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| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
+ | | part number 4 = | ||
| market = Networking | | market = Networking | ||
| first announced = August 22, 2005 | | first announced = August 22, 2005 |
Latest revision as of 16:11, 13 December 2017
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Cavium CN3860-500 EXP | |||||||
General Info | |||||||
Designer | Cavium | ||||||
Manufacturer | TSMC | ||||||
Model Number | CN3860-500 EXP | ||||||
Part Number | CN3860-500BG1521-EXP | ||||||
Market | Networking | ||||||
Introduction | August 22, 2005 (announced) August 22, 2005 (launched) | ||||||
General Specs | |||||||
Family | OCTEON | ||||||
Series | CN3800 | ||||||
Frequency | 500 MHz | ||||||
Microarchitecture | |||||||
ISA | MIPS64 (MIPS) | ||||||
Microarchitecture | cnMIPS | ||||||
Core Name | cnMIPS | ||||||
Process | 130 nm | ||||||
Technology | CMOS | ||||||
Word Size | 64 bit | ||||||
Cores | 16 | ||||||
Threads | 16 | ||||||
Max Memory | 16 GiB | ||||||
Multiprocessing | |||||||
Max SMP | 1-Way (Uniprocessor) | ||||||
Packaging | |||||||
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The CN3860-500 EXP is a 64-bit hexadeca-core MIPS communication microprocessor designed by Cavium and introduced in 2005. This processor, which incorporates sixteen cnMIPS cores, operates at 500 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.
Contents
Cache[edit]
- Main article: cnMIPS § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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Expansions[edit]
Expansion Options
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Networking[edit]
Networking
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Hardware Accelerators[edit]
[Edit/Modify Accelerators Info]
Hardware Accelerators
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Block diagram[edit]
Datasheet[edit]
Facts about "CN3860-500 EXP - Cavium"