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{{cavium title|CN3120-500 EXP}}
 
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| name                = Cavium CN3120-500 EXP
 
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| model number        = CN3120-500 EXP
 
| model number        = CN3120-500 EXP
 
| part number        = CN3120-500BG868-EXP
 
| part number        = CN3120-500BG868-EXP
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| market              = Embedded
 
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| first announced    = January 30, 2006  
 
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| package 0          = HSBGA-868
 
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| package 0 type      = HSBGA
 
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| package 0 pins      = 868
 
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The '''CN3120-500 EXP''' is a {{arch|64}} [[dual-core]] [[MIPS]] communication [[microprocessor]] designed by [[Cavium]] and introduced in [[2006]]. This processor, which incorporates two {{cavium|cnMIPS|l=arch}} cores, operates at 500 MHz. This processor includes a number of hardware accelerators for network processing such as [[compression]] & decompression, [[RegEx]] engine, [[TCP]], and [[QoS]]. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.
 
The '''CN3120-500 EXP''' is a {{arch|64}} [[dual-core]] [[MIPS]] communication [[microprocessor]] designed by [[Cavium]] and introduced in [[2006]]. This processor, which incorporates two {{cavium|cnMIPS|l=arch}} cores, operates at 500 MHz. This processor includes a number of hardware accelerators for network processing such as [[compression]] & decompression, [[RegEx]] engine, [[TCP]], and [[QoS]]. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.

Latest revision as of 15:11, 13 December 2017

Edit Values
Cavium CN3120-500 EXP
octeon cn31xx.png
General Info
DesignerCavium
ManufacturerTSMC
Model NumberCN3120-500 EXP
Part NumberCN3120-500BG868-EXP
MarketEmbedded
IntroductionJanuary 30, 2006 (announced)
May 1, 2006 (launched)
General Specs
FamilyOCTEON
SeriesCN3100
Frequency500 MHz
Microarchitecture
ISAMIPS64 (MIPS)
MicroarchitecturecnMIPS
Core NamecnMIPS
Process130 nm
TechnologyCMOS
Word Size64 bit
Cores2
Threads2
Max Memory4 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Packaging
PackageHSBGA-868 (BGA)
Ball Count868
InterconnectBGA-868

The CN3120-500 EXP is a 64-bit dual-core MIPS communication microprocessor designed by Cavium and introduced in 2006. This processor, which incorporates two cnMIPS cores, operates at 500 MHz. This processor includes a number of hardware accelerators for network processing such as compression & decompression, RegEx engine, TCP, and QoS. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.

Cache[edit]

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$80 KiB
81,920 B
0.0781 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB4-way set associative 
L1D$16 KiB
16,384 B
0.0156 MiB
2x8 KiB64-way set associativeWrite-through
L2$256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
  1x256 KiB8-way set associative 

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR2-667
Supports ECCYes
Max Mem4 GiB
Controllers1
Channels1
Width64 bit
Max Bandwidth4.97 GiB/s
5,089.28 MiB/s
5.336 GB/s
5,336.497 MB/s
0.00485 TiB/s
0.00534 TB/s
Bandwidth
Single 4.97 GiB/s

Optional low-latency controller for content-based processing and meta data

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR2-667
Supports ECCYes
Max Mem2 GiB
Controllers1
Channels1
Width16 bit
Max Bandwidth1.24 GiB/s
1,269.76 MiB/s
1.331 GB/s
1,331.44 MB/s
0.00121 TiB/s
0.00133 TB/s
Bandwidth
Single 1.24 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCI-X
Width32 bit
Clock100 MHz
Rate381.5 MiB/s
USB
Revision2.0
Ports1
Rate60 MB/s
Featureshost / PHY
UART
Ports2
GP I/OYes


Networking[edit]

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
MII
GMIIYes (Ports: 1)
RGMIIYes (Ports: 3)
TDM/PCMYes

Hardware Accelerators[edit]

[Edit/Modify Accelerators Info]

hardware accel icon.svg
Hardware Accelerators
RegEx
RegExYes
Features8 Engines
Networking
TCPYes
QoSYes
Compression
CompressionYes
DecompressionYes

Block diagram[edit]

octeon cn31xx block diagram.png

Datasheet[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=cavium/octeon/cn3120-500bg868-exp&oldid=70199"
Facts about "CN3120-500 EXP - Cavium"
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Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
CN3120-500 EXP - Cavium#package +
base frequency500 MHz (0.5 GHz, 500,000 kHz) +
core count2 +
core namecnMIPS +
designerCavium +
familyOCTEON +
first announcedJanuary 30, 2006 +
first launchedMay 1, 2006 +
full page namecavium/octeon/cn3120-500bg868-exp +
has ecc memory supporttrue +
has hardware accelerators for data compressiontrue +
has hardware accelerators for data decompressiontrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for regular expressiontrue +
has hardware accelerators for tcp packet processingtrue +
instance ofmicroprocessor +
isaMIPS64 +
isa familyMIPS +
l1$ size80 KiB (81,920 B, 0.0781 MiB) +
l1d$ description64-way set associative +
l1d$ size16 KiB (16,384 B, 0.0156 MiB) +
l1i$ description4-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description8-way set associative +
l2$ size0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +
ldateMay 1, 2006 +
main imageFile:octeon cn31xx.png +
manufacturerTSMC +
market segmentEmbedded +
max cpu count1 +
max memory4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) +
max memory bandwidth4.97 GiB/s (5,089.28 MiB/s, 5.336 GB/s, 5,336.497 MB/s, 0.00485 TiB/s, 0.00534 TB/s) + and 1.24 GiB/s (1,269.76 MiB/s, 1.331 GB/s, 1,331.44 MB/s, 0.00121 TiB/s, 0.00133 TB/s) +
max memory channels1 +
microarchitecturecnMIPS +
model numberCN3120-500 EXP +
nameCavium CN3120-500 EXP +
packageHSBGA-868 +
part numberCN3120-500BG868-EXP +
process130 nm (0.13 μm, 1.3e-4 mm) +
seriesCN3100 +
smp max ways1 +
supported memory typeDDR2-667 +
technologyCMOS +
thread count2 +
word size64 bit (8 octets, 16 nibbles) +