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Difference between revisions of "cavium/octeon/cn3120-500bg868-exp"
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{{cavium title|CN3120-500 EXP}} | {{cavium title|CN3120-500 EXP}} | ||
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| name = Cavium CN3120-500 EXP | | name = Cavium CN3120-500 EXP | ||
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| model number = CN3120-500 EXP | | model number = CN3120-500 EXP | ||
| part number = CN3120-500BG868-EXP | | part number = CN3120-500BG868-EXP | ||
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| market = Embedded | | market = Embedded | ||
| first announced = January 30, 2006 | | first announced = January 30, 2006 | ||
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The '''CN3120-500 EXP''' is a {{arch|64}} [[dual-core]] [[MIPS]] communication [[microprocessor]] designed by [[Cavium]] and introduced in [[2006]]. This processor, which incorporates two {{cavium|cnMIPS|l=arch}} cores, operates at 500 MHz. This processor includes a number of hardware accelerators for network processing such as [[compression]] & decompression, [[RegEx]] engine, [[TCP]], and [[QoS]]. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory. | The '''CN3120-500 EXP''' is a {{arch|64}} [[dual-core]] [[MIPS]] communication [[microprocessor]] designed by [[Cavium]] and introduced in [[2006]]. This processor, which incorporates two {{cavium|cnMIPS|l=arch}} cores, operates at 500 MHz. This processor includes a number of hardware accelerators for network processing such as [[compression]] & decompression, [[RegEx]] engine, [[TCP]], and [[QoS]]. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory. | ||
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− | == | + | == Hardware Accelerators == |
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− | + | |regex=Yes | |
− | + | |regex feature=8 Engines | |
− | + | |compression=Yes | |
− | + | |decompression=Yes | |
+ | |tcp=Yes | ||
+ | |qos=Yes | ||
+ | }} | ||
== Block diagram == | == Block diagram == |
Latest revision as of 16:11, 13 December 2017
Edit Values | |||||||
Cavium CN3120-500 EXP | |||||||
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General Info | |||||||
Designer | Cavium | ||||||
Manufacturer | TSMC | ||||||
Model Number | CN3120-500 EXP | ||||||
Part Number | CN3120-500BG868-EXP | ||||||
Market | Embedded | ||||||
Introduction | January 30, 2006 (announced) May 1, 2006 (launched) | ||||||
General Specs | |||||||
Family | OCTEON | ||||||
Series | CN3100 | ||||||
Frequency | 500 MHz | ||||||
Microarchitecture | |||||||
ISA | MIPS64 (MIPS) | ||||||
Microarchitecture | cnMIPS | ||||||
Core Name | cnMIPS | ||||||
Process | 130 nm | ||||||
Technology | CMOS | ||||||
Word Size | 64 bit | ||||||
Cores | 2 | ||||||
Threads | 2 | ||||||
Max Memory | 4 GiB | ||||||
Multiprocessing | |||||||
Max SMP | 1-Way (Uniprocessor) | ||||||
Packaging | |||||||
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The CN3120-500 EXP is a 64-bit dual-core MIPS communication microprocessor designed by Cavium and introduced in 2006. This processor, which incorporates two cnMIPS cores, operates at 500 MHz. This processor includes a number of hardware accelerators for network processing such as compression & decompression, RegEx engine, TCP, and QoS. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.
Contents
Cache[edit]
- Main article: cnMIPS § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Optional low-latency controller for content-based processing and meta data
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options
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Networking[edit]
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Networking
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Hardware Accelerators[edit]
[Edit/Modify Accelerators Info]
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Hardware Accelerators
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Block diagram[edit]
Datasheet[edit]
Facts about "CN3120-500 EXP - Cavium"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | CN3120-500 EXP - Cavium#package + |
base frequency | 500 MHz (0.5 GHz, 500,000 kHz) + |
core count | 2 + |
core name | cnMIPS + |
designer | Cavium + |
family | OCTEON + |
first announced | January 30, 2006 + |
first launched | May 1, 2006 + |
full page name | cavium/octeon/cn3120-500bg868-exp + |
has ecc memory support | true + |
has hardware accelerators for data compression | true + |
has hardware accelerators for data decompression | true + |
has hardware accelerators for network quality of service processing | true + |
has hardware accelerators for regular expression | true + |
has hardware accelerators for tcp packet processing | true + |
instance of | microprocessor + |
isa | MIPS64 + |
isa family | MIPS + |
l1$ size | 80 KiB (81,920 B, 0.0781 MiB) + |
l1d$ description | 64-way set associative + |
l1d$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) + |
ldate | May 1, 2006 + |
main image | ![]() |
manufacturer | TSMC + |
market segment | Embedded + |
max cpu count | 1 + |
max memory | 4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) + |
max memory bandwidth | 4.97 GiB/s (5,089.28 MiB/s, 5.336 GB/s, 5,336.497 MB/s, 0.00485 TiB/s, 0.00534 TB/s) + and 1.24 GiB/s (1,269.76 MiB/s, 1.331 GB/s, 1,331.44 MB/s, 0.00121 TiB/s, 0.00133 TB/s) + |
max memory channels | 1 + |
microarchitecture | cnMIPS + |
model number | CN3120-500 EXP + |
name | Cavium CN3120-500 EXP + |
package | HSBGA-868 + |
part number | CN3120-500BG868-EXP + |
process | 130 nm (0.13 μm, 1.3e-4 mm) + |
series | CN3100 + |
smp max ways | 1 + |
supported memory type | DDR2-667 + |
technology | CMOS + |
thread count | 2 + |
word size | 64 bit (8 octets, 16 nibbles) + |