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Difference between revisions of "amd/k5/amd-ssa-5-75abr"
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{{amd title|AMD-SSA/5-75ABR}} | {{amd title|AMD-SSA/5-75ABR}} | ||
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| name = AMD-SSA/5-75ABR | | name = AMD-SSA/5-75ABR | ||
| no image = | | no image = | ||
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| model number = AMD-SSA/5-75ABR | | model number = AMD-SSA/5-75ABR | ||
| part number = AMD-SSA/5-75ABR | | part number = AMD-SSA/5-75ABR | ||
− | | part number | + | | part number 2 = |
| market = Desktop | | market = Desktop | ||
| first announced = 1996 | | first announced = 1996 | ||
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| thread count = 1 | | thread count = 1 | ||
| max cpus = 1 | | max cpus = 1 | ||
− | | max memory = 4 | + | | max memory = 4 GiB |
| max memory addr = 0xFFFFFFFF | | max memory addr = 0xFFFFFFFF | ||
− | + | ||
| power = | | power = | ||
| v core = 3.525 V | | v core = 3.525 V |
Latest revision as of 15:08, 13 December 2017
Edit Values | |
AMD-SSA/5-75ABR | |
General Info | |
Designer | AMD |
Manufacturer | AMD |
Model Number | AMD-SSA/5-75ABR |
Part Number | AMD-SSA/5-75ABR |
Market | Desktop |
Introduction | 1996 (announced) March 27, 1996 (launched) |
Shop | Amazon |
General Specs | |
Family | K5 |
Series | SSA/5 |
Frequency | 75 MHz |
Bus type | FSB |
Bus speed | 50 MHz |
Bus rate | 50 MT/s |
Clock multiplier | 1.5 |
CPUID | 500 |
Microarchitecture | |
Microarchitecture | K5 |
Core Name | SSA/5 |
Core Family | 5 |
Core Model | 0 |
Core Stepping | 0 |
Process | 500 nm |
Transistors | 4,300,000 |
Technology | CMOS |
Die | 251 mm² |
Word Size | 32 bit |
Cores | 1 |
Threads | 1 |
Max Memory | 4 GiB |
Max Address Mem | 0xFFFFFFFF |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
Vcore | 3.525 V ± 2% |
Tcase | 0 °C – 70 °C |
Tstorage | -65°C – 150 °C |
AMD-SSA/5-75ABR was a 32-bit x86 microprocessor developed by AMD and released in 1996. This processor was the first of AMD's brand new K5 microarchitecture designed entirely in-house. The chip operated at 75 MHz.
Contents
Cache[edit]
- Main article: K5 § Cache
Cache Info [Edit Values] | ||
L1I$ | 16 KiB 16,384 B 0.0156 MiB |
1x16 KiB 4-way set associative |
L1D$ | 8 KiB 8,192 B 0.00781 MiB |
1x8 KiB 4-way set associative |
Graphics[edit]
This SoC has no integrated graphics processing unit.
Features[edit]
- P75 P-Rating
- Auto-power down state
- Stop clock state
Gallery[edit]
See also[edit]
Facts about "AMD-SSA/5-75ABR - AMD"
base frequency | 75 MHz (0.075 GHz, 75,000 kHz) + |
bus rate | 50 MT/s (0.05 GT/s, 50,000 kT/s) + |
bus speed | 50 MHz (0.05 GHz, 50,000 kHz) + |
bus type | FSB + |
clock multiplier | 1.5 + |
core count | 1 + |
core family | 5 + |
core model | 0 + |
core name | SSA/5 + |
core stepping | 0 + |
core voltage | 3.525 V (35.25 dV, 352.5 cV, 3,525 mV) + |
core voltage tolerance | 2% + |
cpuid | 500 + |
designer | AMD + |
die area | 251 mm² (0.389 in², 2.51 cm², 251,000,000 µm²) + |
family | K5 + |
first announced | 1996 + |
first launched | March 27, 1996 + |
full page name | amd/k5/amd-ssa-5-75abr + |
instance of | microprocessor + |
l1d$ description | 4-way set associative + |
l1d$ size | 8 KiB (8,192 B, 0.00781 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
ldate | March 27, 1996 + |
main image | + |
manufacturer | AMD + |
market segment | Desktop + |
max case temperature | 343.15 K (70 °C, 158 °F, 617.67 °R) + |
max cpu count | 1 + |
max memory | 4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) + |
max memory address | 0xFFFFFFFF + |
max storage temperature | 423.15 K (150 °C, 302 °F, 761.67 °R) + |
microarchitecture | K5 + |
min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
min storage temperature | 208.15 K (-65 °C, -85 °F, 374.67 °R) + |
model number | AMD-SSA/5-75ABR + |
name | AMD-SSA/5-75ABR + |
part number | AMD-SSA/5-75ABR + |
process | 500 nm (0.5 μm, 5.0e-4 mm) + |
processor p-rating | P75 + |
series | SSA/5 + |
smp max ways | 1 + |
technology | CMOS + |
thread count | 1 + |
transistor count | 4,300,000 + |
word size | 32 bit (4 octets, 8 nibbles) + |