From WikiChip
Difference between revisions of "amd/k6/amd-k6-200alr"
m (Bot: Automated text replacement (-\| electrical += Yes +)) |
m (Bot: replacing deprecated (and now obselete) {{mpu features}} with {{x86 features}}) |
||
Line 100: | Line 100: | ||
== Features == | == Features == | ||
− | {{ | + | {{x86 features |
| mmx = true | | mmx = true | ||
}} | }} |
Revision as of 14:45, 13 December 2017
Template:mpu AMD-K6-200ALR was a 32-bit x86 microprocessor designed by AMD and introduced in early 1997. This chip, which was based on AMD's new K6 microarchitecture, operated at 200 MHz and dissipated a maximum of 20 W.
Contents
Cache
- Main article: K6 § Cache
L2$ can be 256 KiB to 1 MiB, depending on manufacturer and motherboard model. L2$ is off-chip.
Cache Info [Edit Values] | ||
L1I$ | 32 KiB 32,768 B 0.0313 MiB |
1x32 KiB 2-way set associative |
L1D$ | 32 KiB 32,768 B 0.0313 MiB |
1x32 KiB 2-way set associative |
Graphics
This SoC has no integrated graphics processing unit.
Features
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
|
||
|
- Auto-power down state
- Stop clock state
Documents
DataSheet
- AMD-K6 MMX Enhanced Processor Multimedia Technology; Publication #20695 Revision E/0; June 1997
Facts about "AMD-K6-200ALR - AMD"
l1d$ description | 2-way set associative + |
l1d$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l1i$ description | 2-way set associative + |
l1i$ size | 32 KiB (32,768 B, 0.0313 MiB) + |