From WikiChip
Difference between revisions of "intel/xeon gold/6146"
Line 224: | Line 224: | ||
{{benchmarks main | {{benchmarks main | ||
| | | | ||
− | {{benchmark entry}} | + | {{benchmark entry |
+ | |type=spec | ||
+ | |test_link=https://www.spec.org/cpu2017/results/res2017q4/cpu2017-20171031-00414.html | ||
+ | |test_timestamp=2017-10-22 23:24:41-0400 | ||
+ | |chip_count=2 | ||
+ | |core_count=24 | ||
+ | |copies_count=48 | ||
+ | |vendor=Cisco Systems | ||
+ | |system=Cisco UCS B200 M5 (Intel Xeon Gold 6146, 3.20GHz) | ||
+ | |SPECrate2017_fp_base=168 | ||
+ | |SPECrate2017_fp_peak=171 | ||
+ | }} | ||
}} | }} | ||
[[Category:microprocessor models by intel based on skylake extreme core count die]] | [[Category:microprocessor models by intel based on skylake extreme core count die]] |
Revision as of 02:14, 24 November 2017
Template:mpu Xeon Gold 6146 is a 64-bit dodeca-core x86 multi-socket high performance server microprocessor introduced by Intel in mid-2017. This chip supports up to 4-way multiprocessing. The Gold 6146, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm+ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 3.2 GHz with a TDP of 165 W and a turbo boost frequency of up to 4.2 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.
Cache
- Main article: Skylake § Cache
The Xeon Gold 6146 features a considerably larger non-default 24.75 MiB of L3, a size that would normally be found on an 18-core part.
![]() |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
||||||||||||||||||||||||||||||||||||
|
Memory controller
![]() |
Integrated Memory Controller
|
|||||||||||||
|
Expansions
![]() |
Expansion Options
|
|||||||
|
Features
[Edit/Modify Supported Features]
![]() |
Supported x86 Extensions & Processor Features
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
Frequencies
- See also: Intel's CPU Frequency Behavior
Mode | Base | Turbo Frequency/Active Cores | |||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | ||
Normal | 3,200 MHz | 4,200 MHz | 4,200 MHz | 4,100 MHz | 4,100 MHz | 4,000 MHz | 4,000 MHz | 4,000 MHz | 4,000 MHz | 3,900 MHz | 3,900 MHz | 3,900 MHz | 3,900 MHz |
AVX2 | 2,600 MHz | 3,600 MHz | 3,600 MHz | 3,400 MHz | 3,400 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz | 3,300 MHz |
AVX512 | 2,100 MHz | 3,500 MHz | 3,500 MHz | 3,300 MHz | 3,300 MHz | 3,100 MHz | 3,100 MHz | 3,100 MHz | 3,100 MHz | 2,700 MHz | 2,700 MHz | 2,700 MHz | 2,700 MHz |
Benchmarks
Facts about "Xeon Gold 6146 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Gold 6146 - Intel#io + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables + and Transactional Synchronization Extensions + |
has intel enhanced speedstep technology | true + |
has intel speed shift technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
l1$ size | 768 KiB (786,432 B, 0.75 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 24.75 MiB (25,344 KiB, 25,952,256 B, 0.0242 GiB) + |
max memory bandwidth | 119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) + |
max memory channels | 6 + |
max pcie lanes | 48 + |
supported memory type | DDR4-2666 + |