Semiconductor & Computer Engineering
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{{intel title|ETANN}} | {{intel title|ETANN}} | ||
'''ETANN''' ('''Electronically Trainable Analog Neural Network''') was the [[first]] commercial [[neural processor]], introduced by [[Intel]] in [[1992]]. Implemented on a [[1.0 µm process]], this chip incorporated 64 analog neurons and 10,240 analog synapses. | '''ETANN''' ('''Electronically Trainable Analog Neural Network''') was the [[first]] commercial [[neural processor]], introduced by [[Intel]] in [[1992]]. Implemented on a [[1.0 µm process]], this chip incorporated 64 analog neurons and 10,240 analog synapses. | ||
| + | |||
| + | == Overview == | ||
| + | The ETANN was originally announced at the [[1989]] International Joint Conference on Neural Networks (IJCNN). The chip was implemented using an analog nonvolatile floating gate technology on Intel's CHMOS-III 1µm nonvolatile memory technology. The chip integrates a total of 64 analog neurons and 1024 analog nonvolatile synapses. The network calculated the [[dot product]] between the 64x64 nonvolatile EEPROM analog synaptic weight array and a 64-element analog input vector. The chip was reported the calculations to exceed 1.3 billion interconnections per second. | ||
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| + | == Die == | ||
| + | * CHMOS-III 1µm nonvolatile memory technology | ||
| + | * 93.15 mm² die size | ||
| + | ** 8.1 mm x 11.5 mm | ||
| + | |||
| + | Floor plan: | ||
| + | |||
| + | ::[[File:ETANN floor plan.png|500px]] | ||
Revision as of 03:06, 20 November 2017
ETANN (Electronically Trainable Analog Neural Network) was the first commercial neural processor, introduced by Intel in 1992. Implemented on a 1.0 µm process, this chip incorporated 64 analog neurons and 10,240 analog synapses.
Overview
The ETANN was originally announced at the 1989 International Joint Conference on Neural Networks (IJCNN). The chip was implemented using an analog nonvolatile floating gate technology on Intel's CHMOS-III 1µm nonvolatile memory technology. The chip integrates a total of 64 analog neurons and 1024 analog nonvolatile synapses. The network calculated the dot product between the 64x64 nonvolatile EEPROM analog synaptic weight array and a 64-element analog input vector. The chip was reported the calculations to exceed 1.3 billion interconnections per second.
Die
- CHMOS-III 1µm nonvolatile memory technology
- 93.15 mm² die size
- 8.1 mm x 11.5 mm
Floor plan:
