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Difference between revisions of "qualcomm/centriq/2460"
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'''Centriq 2460''' is a {{arch|64}} [[48-core]] [[ARM]] high-performance server microprocessor designed by [[Qualcomm]] and introduced in late 2017.This processor, which is based on the {{qualcomm|Falkor|l=arch}} microarchitecture, is fabricated on [[Samsung]]'s [[10 nm process|10LPE process]]. The 2460 has a based frequency of 2.2 GHz with a TDP of 120 W and a turbo frequency of 2.6 GHz. This chip supports up to 768 GiB of hexa-channel DDR4-2666 memory.
 
'''Centriq 2460''' is a {{arch|64}} [[48-core]] [[ARM]] high-performance server microprocessor designed by [[Qualcomm]] and introduced in late 2017.This processor, which is based on the {{qualcomm|Falkor|l=arch}} microarchitecture, is fabricated on [[Samsung]]'s [[10 nm process|10LPE process]]. The 2460 has a based frequency of 2.2 GHz with a TDP of 120 W and a turbo frequency of 2.6 GHz. This chip supports up to 768 GiB of hexa-channel DDR4-2666 memory.
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== Cache ==
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{{main|qualcomm/microarchitectures/falkor#Memory_Hierarchy|l1=Falkor § Cache}}
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{{cache size
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|l1 cache=4.5 MiB
 +
|l1i cache=3 MiB
 +
|l1i break=48x64 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=1.5 MiB
 +
|l1d break=48x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=write-through
 +
|l2 cache=12 MiB
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|l2 break=20x512 KiB
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|l2 desc=8-way set associative
 +
|l3 cache=60 MiB
 +
|l3 break=12x5 MiB
 +
|l3 desc=20-way set associative
 +
}}

Revision as of 03:43, 9 November 2017

Template:mpu Centriq 2460 is a 64-bit 48-core ARM high-performance server microprocessor designed by Qualcomm and introduced in late 2017.This processor, which is based on the Falkor microarchitecture, is fabricated on Samsung's 10LPE process. The 2460 has a based frequency of 2.2 GHz with a TDP of 120 W and a turbo frequency of 2.6 GHz. This chip supports up to 768 GiB of hexa-channel DDR4-2666 memory.

Cache

Main article: Falkor § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$4.5 MiB
4,608 KiB
4,718,592 B
L1I$3 MiB
3,072 KiB
3,145,728 B
48x64 KiB8-way set associative 
L1D$1.5 MiB
1,536 KiB
1,572,864 B
48x32 KiB8-way set associativewrite-through
L2$12 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
  20x512 KiB8-way set associative 
L3$60 MiB
61,440 KiB
62,914,560 B
0.0586 GiB
  12x5 MiB20-way set associative 
Retrieved from "https://en.wikichip.org/w/index.php?title=qualcomm/centriq/2460&oldid=66907"
Facts about "Centriq 2460 - Qualcomm"
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l1$ size4,608 KiB (4,718,592 B, 4.5 MiB) +
l1d$ description8-way set associative +
l1d$ size1,536 KiB (1,572,864 B, 1.5 MiB) +
l1i$ description8-way set associative +
l1i$ size3,072 KiB (3,145,728 B, 3 MiB) +
l2$ description8-way set associative +
l2$ size12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) +
l3$ description20-way set associative +
l3$ size60 MiB (61,440 KiB, 62,914,560 B, 0.0586 GiB) +