From WikiChip
Difference between revisions of "qualcomm/centriq/2452"
Line 31: | Line 31: | ||
}} | }} | ||
'''Centriq 2452''' is a {{arch|64}} [[46-core]] [[ARM]] high-performance server microprocessor designed by [[Qualcomm]] and introduced in late 2017. This processor, which is based on the {{qualcomm|Falkor|l=arch}} microarchitecture, is fabricated on [[Samsung]]'s [[10 nm process|10LPE process]]. The 2452 has a based frequency of 2.2 GHz with a TDP of 120 W and a turbo frequency of 2.6 GHz. This chip supports up to 768 GiB of hexa-channel DDR4-2666 memory. | '''Centriq 2452''' is a {{arch|64}} [[46-core]] [[ARM]] high-performance server microprocessor designed by [[Qualcomm]] and introduced in late 2017. This processor, which is based on the {{qualcomm|Falkor|l=arch}} microarchitecture, is fabricated on [[Samsung]]'s [[10 nm process|10LPE process]]. The 2452 has a based frequency of 2.2 GHz with a TDP of 120 W and a turbo frequency of 2.6 GHz. This chip supports up to 768 GiB of hexa-channel DDR4-2666 memory. | ||
+ | |||
+ | == Cache == | ||
+ | {{main|qualcomm/microarchitectures/falkor#Memory_Hierarchy|l1=Falkor § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=4.3125 MiB | ||
+ | |l1i cache=2.875 MiB | ||
+ | |l1i break=46x64 KiB | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1d cache=1.4375 MiB | ||
+ | |l1d break=46x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d policy=write-through | ||
+ | |l2 cache=11.5 MiB | ||
+ | |l2 break=20x512 KiB | ||
+ | |l2 desc=8-way set associative | ||
+ | |l3 cache=57.5 MiB | ||
+ | |l3 break=11.5x5 MiB | ||
+ | |l3 desc=20-way set associative | ||
+ | }} |
Revision as of 03:42, 9 November 2017
Template:mpu Centriq 2452 is a 64-bit 46-core ARM high-performance server microprocessor designed by Qualcomm and introduced in late 2017. This processor, which is based on the Falkor microarchitecture, is fabricated on Samsung's 10LPE process. The 2452 has a based frequency of 2.2 GHz with a TDP of 120 W and a turbo frequency of 2.6 GHz. This chip supports up to 768 GiB of hexa-channel DDR4-2666 memory.
Cache
- Main article: Falkor § Cache
![]() |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
||||||||||||||||||||||||||||||||||||
|
Facts about "Centriq 2452 - Qualcomm"
l1$ size | 4,416 KiB (4,521,984 B, 4.313 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 1,472 KiB (1,507,328 B, 1.438 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 2,944 KiB (3,014,656 B, 2.875 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 11.5 MiB (11,776 KiB, 12,058,624 B, 0.0112 GiB) + |
l3$ description | 20-way set associative + |
l3$ size | 57.5 MiB (58,880 KiB, 60,293,120 B, 0.0562 GiB) + |