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Difference between revisions of "qualcomm/centriq/2434"
< qualcomm‎ | centriq

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== Cache ==
 
== Cache ==
 
{{main|qualcomm/microarchitectures/falkor#Memory_Hierarchy|l1=Falkor § Cache}}
 
{{main|qualcomm/microarchitectures/falkor#Memory_Hierarchy|l1=Falkor § Cache}}
−
{{cache size}}
+
{{cache size
 +
|l1 cache=3.75 MiB
 +
|l1i cache=2.5 MiB
 +
|l1i break=40x64 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=1.25 MiB
 +
|l1d break=40x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=write-through
 +
|l2 cache=10 MiB
 +
|l2 break=20x512 KiB
 +
|l2 desc=8-way set associative
 +
|l3 cache=50 MiB
 +
|l3 break=10x5 MiB
 +
|l3 desc=20-way set associative
 +
}}

Revision as of 03:40, 9 November 2017

Template:mpu Centriq 2434 is a 64-bit 40-core ARM high-performance server microprocessor designed by Qualcomm and introduced in late 2017. This processor, which is based on the Falkor microarchitecture, is fabricated on Samsung's 10LPE process. The 2434 has a based frequency of 2.3 GHz with a TDP of 110 W and a turbo frequency of 2.5 GHz. This chip supports up to 768 GiB of hexa-channel DDR4-2666 memory.

Cache

Main article: Falkor § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$3.75 MiB
3,840 KiB
3,932,160 B
L1I$2.5 MiB
2,560 KiB
2,621,440 B
40x64 KiB8-way set associative 
L1D$1.25 MiB
1,280 KiB
1,310,720 B
40x32 KiB8-way set associativewrite-through
L2$10 MiB
10,240 KiB
10,485,760 B
0.00977 GiB
  20x512 KiB8-way set associative 
L3$50 MiB
51,200 KiB
52,428,800 B
0.0488 GiB
  10x5 MiB20-way set associative 
Retrieved from "https://en.wikichip.org/w/index.php?title=qualcomm/centriq/2434&oldid=66905"
Facts about "Centriq 2434 - Qualcomm"
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l1$ size3,840 KiB (3,932,160 B, 3.75 MiB) +
l1d$ description8-way set associative +
l1d$ size1,280 KiB (1,310,720 B, 1.25 MiB) +
l1i$ description8-way set associative +
l1i$ size2,560 KiB (2,621,440 B, 2.5 MiB) +
l2$ description8-way set associative +
l2$ size10 MiB (10,240 KiB, 10,485,760 B, 0.00977 GiB) +
l3$ description20-way set associative +
l3$ size50 MiB (51,200 KiB, 52,428,800 B, 0.0488 GiB) +