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|channels=4 | |channels=4 |
Revision as of 01:09, 3 November 2017
Template:mpu PEZY-SC3 (PEZY Super Computer 3) is fourth generation many-core microprocessor planned by PEZY. The SC3 incorporates 8,096 cores, four times as many cores as its predecessor.
Planned to be fabricated on TSMC's 7 nm process, PEZY-SC3 operates at 1.33 GHz and consume around 400 W while delivering performance in the order of 87.2 TFLOPS (HP), 43.6 TFLOPS (SP), and 21.8 TFLOPS (DP).
Memory controller
For main memory, the PEZY-SC3 supports 4 channels of 64-bit DDR4-3600 memory with ECC support for a total aggregated bandwidth of 107.3 GiB/s
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Integrated Memory Controller
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In addition to main memory bandwidth, the PEZY-SC3 supports Wide-IO with a width of 2,048 bit, twice the twice of the SC2. As with the SC2, the SC3 will use ThruChip Interface (TCI) interfaces in order to communicate with the TCI-DRAM chips. This chip incorporates 8 interfaces, operating at 3 GHz for a bandwidth of 1.525 TB/s per interface for a total aggregated bandwidth of 12.2 TB/s - over 5.8 the bandwidth of its predecessor.
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Integrated Memory Controller
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Expansions
With the SC3, PEZY plans to replace the previous PCIe interface with a custom optics interface featuring 128 lanes supporting a bandwidth of 256 GB/s.
has ecc memory support | true + and false + |
max memory bandwidth | 107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) + and 11,448.32 GiB/s (11,723,079.68 MiB/s, 12,292.54 GB/s, 12,292,539.999 MB/s, 11.18 TiB/s, 12.293 TB/s) + |
max memory channels | 4 + and 8 + |
supported memory type | DDR4-3600 + |