Semiconductor & Computer Engineering
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Difference between revisions of "Template:cache size"
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| − | <div style="background:#f9f9f9; margin: 10px; padding: 5px; border: 1px solid #a7d7f9; display: inline-block; width: | + | <div style="background:#f9f9f9; margin: 10px 2px 10px 2px; padding: 5px; border: 1px solid #a7d7f9; display: inline-block; width: 700px;"> |
<span style="margin: -12px -2px; float: right;">[[Special:FormEdit/cache size/{{FULLPAGENAME}}|<nowiki>[Edit/Modify Cache Info]</nowiki>]]</span> | <span style="margin: -12px -2px; float: right;">[[Special:FormEdit/cache size/{{FULLPAGENAME}}|<nowiki>[Edit/Modify Cache Info]</nowiki>]]</span> | ||
<table> | <table> | ||
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<tr style="vertical-align:top;"><td> | <tr style="vertical-align:top;"><td> | ||
<table class="tl1" style="margin-left: 10px;"><!-- | <table class="tl1" style="margin-left: 10px;"><!-- | ||
| − | -->{{#if: | + | -->{{#if: {{{l1 cache|}}} | <tr><th style="min-width: 35px;">L1$</th><td>[[l1$ size::{{{l1 cache}}}]]</td><td><table><!-- |
| − | -->{{#if: {{{l1i cache|}}} | <tr><th style="text-align: center; min-width: 50px;">L1I$</th><td style="min-width: 50px;">[[l1i$ size::{{{l1i cache}}}]]</td><td style="min-width: 75px;">{{{l1i break}}}</td><td style="min-width: 175px;">[[l1i$ description::{{{l1i desc}}}]]</td><td>{{{l1i policy}}}</td></tr> }}<!-- | + | -->{{#if: {{{l1i cache|}}} | <tr><th style="text-align: center; min-width: 50px;">L1I$</th><td style="min-width: 50px;">[[l1i$ size::{{{l1i cache}}}]]</td><td style="min-width: 75px;">{{{l1i break| }}}</td><td style="min-width: 175px;">{{#if: {{{l1i desc|}}}|[[l1i$ description::{{{l1i desc}}}]]| }}</td><td>{{#if:{{{l1i policy|}}}|{{{l1i policy}}}| }}</td></tr> }}<!-- |
| − | -->{{#if: {{{l1d cache|}}} | <tr><th style="text-align: center; min-width: 50px;">L1D$</th><td>[[l1d$ size::{{{l1d cache}}}]]</td><td>{{{l1d break}}}</td><td style="min-width: 175px;">[[l1d$ description::{{{l1d desc}}}]]</td><td>{{{l1d policy}}}</td></tr> }}<!-- | + | -->{{#if: {{{l1d cache|}}} | <tr><th style="text-align: center; min-width: 50px;">L1D$</th><td>[[l1d$ size::{{{l1d cache}}}]]</td><td style="min-width: 75px;">{{{l1d break| }}}</td><td style="min-width: 175px;">{{#if:{{{l1d desc|}}}|[[l1d$ description::{{{l1d desc}}}]]| }}</td><td>{{#if:{{{l1d policy|}}}|{{{l1d policy}}}| }}</td></tr> }}<!-- |
| − | -->{{#if: {{#if: {{{l1i cache|}}}{{{l1d cache|}}} | | + | -->{{#if: {{#if:{{{l1i cache|}}}{{{l1d cache|}}}||1}} | <tr><th style="text-align: center; min-width: 50px;"> </th><td style="min-width: 50px;"> </td><td style="min-width: 75px;">{{{l1 break}}}</td><td style="min-width: 175px;">{{#if: {{{l1 desc|}}} | [[l1$ description::{{{l1 desc}}}]] | }}</td><td>{{#if:{{{l1 policy|}}}|{{{l1 policy}}}| }}</td></tr> }}<!-- |
| − | --></table></td></tr | + | --></table></td></tr>{{#if: {{{l2 cache|}}}|<tr><td colspan="4"><hr></td></tr>}} }}<!-- |
| − | + | -->{{#if: {{{l2 cache|}}} | <tr><th style="min-width: 35px;">L2$</th><td>[[l2$ size::{{{l2 cache}}}]]</td><td><table><!-- | |
| − | + | -->{{#if: {{{l2i cache|}}} | <tr><th style="text-align: center; min-width: 50px;">L2I$</th><td style="min-width: 50px;">[[l2i$ size::{{{l2i cache}}}]]</td><td style="min-width: 75px;">{{{l2i break}}}</td><td style="min-width: 175px;">[[l2i$ description::{{{l2i desc}}}]]</td><td>{{#if:{{{l2i policy|}}}|{{{l2i policy}}}| }}</td></tr> }}<!-- | |
| − | + | -->{{#if: {{{l2d cache|}}} | <tr><th style="text-align: center; min-width: 50px;">L2D$</th><td>[[l2d$ size::{{{l2d cache}}}]]</td><td style="min-width: 75px;">{{{l2d break}}}</td><td style="min-width: 175px;">{{#if: {{{l2d desc|}}} | [[l2d$ description::{{{l2d desc}}}]] | }}</td><td>{{#if:{{{l2d policy|}}}|{{{l2d policy}}}| }}</td></tr> }}<!-- | |
| − | + | -->{{#if: {{#if: {{{l2i cache|}}}{{{l2d cache|}}}||1}} | <tr><th style="text-align: center; min-width: 50px;"> </th><td style="min-width: 50px;"> </td><td style="min-width: 75px;">{{{l2 break| }}}</td><td style="min-width: 175px;">{{#if: {{{l2 desc|}}} | [[l2$ description::{{{l2 desc}}}]] | }}</td><td>{{#if:{{{l2 policy|}}}|{{{l2 policy}}}| }}</td></tr> }}<!-- | |
| − | --> | + | --></table></td></tr>{{#if: {{{l3 cache|}}}|<tr><td colspan="4"><hr></td></tr>}} }}<!-- |
| − | + | -->{{#if: {{{l3 cache|}}} | <tr><th style="min-width: 35px;">L3$</th><td>[[l3$ size::{{{l3 cache}}}]]</td><td><table><tr><th style="text-align: center; min-width: 50px;"> </th><td style="min-width: 50px;"> </td><td style="min-width: 75px;">{{#if:{{{l3 break|}}}|{{{l3 break}}}| }}</td><td style="min-width: 175px;">{{#if: {{{l3 desc|}}} | [[l3$ description::{{{l3 desc}}}]] | }}</td><td>{{#if:{{{l3 policy|}}}|{{{l3 policy}}}| }}</td></tr></table></td></tr>{{#if: {{{l4 cache|}}}|<tr><td colspan="4"><hr></td></tr>}} }}<!-- | |
| − | + | -->{{#if: {{{l4 cache|}}} | <tr><th style="min-width: 35px;">L4$</th><td>[[l4$ size::{{{l4 cache}}}]]</td><td><table><tr><th style="text-align: center; min-width: 50px;"> </th><td style="min-width: 50px;"> </td><td style="min-width: 75px;">{{#if:{{{l4 break|}}}|{{{l4 break}}}| }}</td><td style="min-width: 175px;">{{#if: {{{l4 desc|}}} | [[l4$ description::{{{l4 desc}}}]] | }}</td><td>{{#if:{{{l4 policy|}}}|{{{l4 policy}}}| }}</td></tr></table></td></tr>{{#if: {{{mobo cache|}}}|<tr><td colspan="4"><hr></td></tr>}} }}<!-- | |
| − | + | -->{{#if: {{{mobo cache|}}} | <tr><th style="min-width: 35px;">Mobo</th><td>[[mobo$ size::{{{mobo cache}}}]]</td><td><table><tr><th style="text-align: center; min-width: 50px;"> </th><td style="min-width: 50px;"> </td><td style="min-width: 75px;">{{{mobo break}}}</td><td style="min-width: 175px;">{{#if: {{{mobo desc|}}} | [[mobo$ description::{{{mobo desc}}}]] | }}</td><td>{{#if:{{{mobo policy|}}}|{{{mobo policy}}}| }}</td></tr></table></td></tr> }}<!-- | |
--></table> | --></table> | ||
</td> | </td> | ||
Latest revision as of 21:56, 2 November 2017
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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