From WikiChip
Difference between revisions of "freescale/qoriq/p1013"
< freescale/qoriq

Line 25: Line 25:
 
|package module 1={{packages/freescale/te-pbga-ii-689}}
 
|package module 1={{packages/freescale/te-pbga-ii-689}}
 
}}
 
}}
 +
'''QorIQ P1013''' is a {{arch|32}} embedded [[POWER]] microprocessor introduced by [[Freescale]] in late [[2009]]. This networking/embedded processor, which is based on the {{freescale|e500|l=arch}} microarchitecture and is fabricated on a [[45 nm SOI process]], operates at 1,067 MHz and supports 64-bit DDR3-800 memory.
 +
 +
== Cache ==
 +
{{main|freescale/microarchitectures/e500#Memory_Hierarchy|l1=e500 § Cache}}
 +
{{cache size
 +
|l1 cache=64 KiB
 +
|l1i cache=32 KiB
 +
|l1i break=1x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=32 KiB
 +
|l1d break=1x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=
 +
|l2 cache=256 KiB
 +
|l2 break=1x256 KiB
 +
|l2 desc=8-way set associative
 +
|l2 policy=Write-through
 +
}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR3-800
 +
|ecc=Yes
 +
|controllers=1
 +
|channels=1
 +
|width=64 bit
 +
|max bandwidth=5.96 GiB/s
 +
|bandwidth schan=5.96 GiB/s
 +
}}
 +
 +
== Expansions ==
 +
* 3x 10/100/1000 Ethernet with 2x SGMII
 +
* x4+1 PCIe 1.0 interface
 +
* 2x USB 2.0
 +
* SD/MMC
 +
* SPI
 +
* 2x I2C
 +
* UART
 +
 +
== Block Diagram ==
 +
: [[File:qoriq p1013 block diagram.png|800px]]
 +
 +
== Documents ==
 +
* [[:File:p1013-p1022.pdf|P1013/P1022 Product Brief]]

Revision as of 19:52, 31 October 2017

Template:mpu QorIQ P1013 is a 32-bit embedded POWER microprocessor introduced by Freescale in late 2009. This networking/embedded processor, which is based on the e500 microarchitecture and is fabricated on a 45 nm SOI process, operates at 1,067 MHz and supports 64-bit DDR3-800 memory.

Cache

Main article: e500 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$64 KiB
65,536 B
0.0625 MiB
L1I$32 KiB
32,768 B
0.0313 MiB
1x32 KiB8-way set associative 
L1D$32 KiB
32,768 B
0.0313 MiB
1x32 KiB8-way set associative 
L2$256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
  1x256 KiB8-way set associativeWrite-through

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-800
Supports ECCYes
Controllers1
Channels1
Width64 bit
Max Bandwidth5.96 GiB/s
6,103.04 MiB/s
6.4 GB/s
6,399.501 MB/s
0.00582 TiB/s
0.0064 TB/s
Bandwidth
Single 5.96 GiB/s

Expansions

  • 3x 10/100/1000 Ethernet with 2x SGMII
  • x4+1 PCIe 1.0 interface
  • 2x USB 2.0
  • SD/MMC
  • SPI
  • 2x I2C
  • UART

Block Diagram

qoriq p1013 block diagram.png

Documents

Retrieved from "https://en.wikichip.org/w/index.php?title=freescale/qoriq/p1013&oldid=66492"
Facts about "QorIQ P1013 - Freescale"
RDF feed
has ecc memory supporttrue +
l1$ size64 KiB (65,536 B, 0.0625 MiB) +
l1d$ description8-way set associative +
l1d$ size32 KiB (32,768 B, 0.0313 MiB) +
l1i$ description8-way set associative +
l1i$ size32 KiB (32,768 B, 0.0313 MiB) +
l2$ description8-way set associative +
l2$ size0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +
max memory bandwidth5.96 GiB/s (6,103.04 MiB/s, 6.4 GB/s, 6,399.501 MB/s, 0.00582 TiB/s, 0.0064 TB/s) +
max memory channels1 +
supported memory typeDDR3-800 +