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Difference between revisions of "freescale/qoriq/p1014"
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{{freescale title|QorIQ P1014}} | {{freescale title|QorIQ P1014}} | ||
{{mpu | {{mpu | ||
− | |name=P1014 | + | |name=QorIQ P1014 |
|image=qoriq p1014.png | |image=qoriq p1014.png | ||
|designer=Freescale | |designer=Freescale | ||
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|isa family=Power | |isa family=Power | ||
|microarch=e500 | |microarch=e500 | ||
− | |core name=e500 | + | |core name=e500 v2 |
|process=45 nm | |process=45 nm | ||
|technology=CMOS | |technology=CMOS | ||
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|core count=1 | |core count=1 | ||
|thread count=1 | |thread count=1 | ||
− | |power= | + | |power=1.13 W |
|tjunc min=0 °C | |tjunc min=0 °C | ||
|tjunc max=125 °C | |tjunc max=125 °C | ||
|package module 1={{packages/freescale/te-pbga-ii-689}} | |package module 1={{packages/freescale/te-pbga-ii-689}} | ||
+ | |package module 2={{packages/freescale/te-pbga-425}} | ||
}} | }} | ||
'''QorIQ P1014''' is a {{arch|32}} embedded [[POWER]] microprocessor introduced by [[Freescale]] in [[2008]]. This networking/embedded processor, which is based on the {{freescale|e500|l=arch}} microarchitecture and is fabricated on a [[45 nm SOI process]], operates at 800 MHz and supports 16-bit DDR3-800 memory. | '''QorIQ P1014''' is a {{arch|32}} embedded [[POWER]] microprocessor introduced by [[Freescale]] in [[2008]]. This networking/embedded processor, which is based on the {{freescale|e500|l=arch}} microarchitecture and is fabricated on a [[45 nm SOI process]], operates at 800 MHz and supports 16-bit DDR3-800 memory. |
Revision as of 00:02, 30 October 2017
Template:mpu QorIQ P1014 is a 32-bit embedded POWER microprocessor introduced by Freescale in 2008. This networking/embedded processor, which is based on the e500 microarchitecture and is fabricated on a 45 nm SOI process, operates at 800 MHz and supports 16-bit DDR3-800 memory.
Cache
- Main article: e500 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
- 2x 10/100/1000 Eithernet with SGMII
- 2x PCIe 1.0a controllers with 2 SerDes
Block Diagram
Facts about "QorIQ P1014 - Freescale"
has ecc memory support | true + |
l1$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) + |
max memory bandwidth | 1.49 GiB/s (1,525.76 MiB/s, 1.6 GB/s, 1,599.875 MB/s, 0.00146 TiB/s, 0.0016 TB/s) + |
max memory channels | 1 + |
supported memory type | DDR3-800 + |