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Difference between revisions of "freescale/qoriq/p2020"
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== Documents ==
 
== Documents ==
 
* [[:File:QorIQ P2.pdf|QorIQ P2 Series Product Brief]]
 
* [[:File:QorIQ P2.pdf|QorIQ P2 Series Product Brief]]
 +
* [[:File:P2 Family App Bro.pdf|P2 Platform Series]]

Revision as of 21:35, 24 October 2017

Template:mpu QorIQ P2020 is a 32-bit embedded dual-core POWER microprocessor introduced by Freescale in 2008. This networking/embedded processor, which is based on the e500 microarchitecture and is fabricated on a 45 nm SOI process, operates at 1.2 GHz and supports 64-bit DDR2/3 memory.

Cache

Main article: e500 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associative 
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  1x512 KiB8-way set associativeWrite-through

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-800
Supports ECCYes
Controllers1
Channels1
Width64 bit
Max Bandwidth5.96 GiB/s
6,103.04 MiB/s
6.4 GB/s
6,399.501 MB/s
0.00582 TiB/s
0.0064 TB/s
Bandwidth
Single 5.96 GiB/s

Expansions

  • 3x 10/100/1000 Eithernet with SGMII
  • 3x PCIe 1.0a controllers with 2 SerDes
  • 1x USB 2.0
  • SD/MMC
  • SPI
  • 2x I2C
  • UART
  • SEC 3.1 Security Acceleration

Block Diagram

qoriq p2010 block diagram.png

Documents

Retrieved from "https://en.wikichip.org/w/index.php?title=freescale/qoriq/p2020&oldid=66226"
Facts about "QorIQ P2020 - Freescale"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
QorIQ P2020 - Freescale#package +
base frequency800 MHz (0.8 GHz, 800,000 kHz) +, 1,200 MHz (1.2 GHz, 1,200,000 kHz) + and 1,333 MHz (1.333 GHz, 1,333,000 kHz) +
core count2 +
core namee500 v2 +
designerFreescale +
familyQorIQ +
first announcedJune 16, 2008 +
first launched2009 +
full page namefreescale/qoriq/p2020 +
has ecc memory supporttrue +
instance ofmicroprocessor +
isaPower ISA v2.03 +
isa familyPower +
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ description8-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description8-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description8-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
last order2023 +
ldate2009 +
manufacturerIBM +
market segmentNetworking + and Embedded +
max junction temperature398.15 K (125 °C, 257 °F, 716.67 °R) +
max memory bandwidth5.96 GiB/s (6,103.04 MiB/s, 6.4 GB/s, 6,399.501 MB/s, 0.00582 TiB/s, 0.0064 TB/s) +
max memory channels1 +
microarchitecturee500 +
min junction temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
model numberP2020 +
nameP2020 +
packageTE-PBGA-II-689 +
power dissipation8 W (8,000 mW, 0.0107 hp, 0.008 kW) +
process45 nm (0.045 μm, 4.5e-5 mm) +
seriesP2 +
supported memory typeDDR3-800 +
technologyCMOS +
thread count2 +
word size32 bit (4 octets, 8 nibbles) +