Semiconductor & Computer Engineering
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Difference between revisions of "microsoft/scorpio engine"
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|max memory=12 GiB | |max memory=12 GiB | ||
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| − | '''Scorpio Engine''' is a {{arch|64}} [[octa-core]] [[x86]] SoC designed by [[AMD]] and [[Microsoft]] for their ''Xbox One X'' | + | '''Scorpio Engine''' is a {{arch|64}} [[octa-core]] [[x86]] SoC designed by [[AMD]] and [[Microsoft]] for their ''Xbox One X''. The chip features eight {{amd|Enhanced Jaguar|l=arch}} cores operating at 2.3 GHz and a custom GPU operating at 1.172 GHz. This chip supports 12 (24 for Dev) GiB of 12-channel GDDR5-6800 memory. |
| + | |||
| + | == Cache == | ||
| + | {{main|amd/microarchitectures/enhanced_jaguar#Memory_Hierarchy|l1=Enhanced Jaguar § Cache}} | ||
| + | {{cache size | ||
| + | |l1 cache=512 KiB | ||
| + | |l1i cache=256 KiB | ||
| + | |l1i break=8x32 KiB | ||
| + | |l1i desc=2-way set associative | ||
| + | |l1d cache=256 KiB | ||
| + | |l1d break=8x32 KiB | ||
| + | |l1d desc=8-way set associative | ||
| + | |l1d policy=write-back | ||
| + | |l2 cache=4 MiB | ||
| + | |l2 break=2x2 MiB | ||
| + | |l2 desc=16-way set associative | ||
| + | |l2 policy=write-back | ||
| + | }} | ||
| + | |||
| + | == Memory controller == | ||
| + | {{memory controller | ||
| + | |type=GDDR5-6800 | ||
| + | |max mem=12 GiB | ||
| + | |controllers=12 | ||
| + | |channels=12 | ||
| + | |width=384 | ||
| + | |max bandwidth=304 GiB/s | ||
| + | |bandwidth schan=25.33 GiB/s | ||
| + | }} | ||
Revision as of 17:56, 14 September 2017
Template:mpu Scorpio Engine is a 64-bit octa-core x86 SoC designed by AMD and Microsoft for their Xbox One X. The chip features eight Enhanced Jaguar cores operating at 2.3 GHz and a custom GPU operating at 1.172 GHz. This chip supports 12 (24 for Dev) GiB of 12-channel GDDR5-6800 memory.
Cache
- Main article: Enhanced Jaguar § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Facts about "Scorpio Engine - Microsoft"
| has ecc memory support | false + |
| l1$ size | 512 KiB (524,288 B, 0.5 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l1i$ description | 2-way set associative + |
| l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
| l2$ description | 16-way set associative + |
| l2$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
| max memory bandwidth | 304 GiB/s (311,296 MiB/s, 326.418 GB/s, 326,417.514 MB/s, 0.297 TiB/s, 0.326 TB/s) + |
| max memory channels | 12 + |
| supported memory type | GDDR5-6800 + |