From WikiChip
Difference between revisions of "hisilicon/k3/k3v1"
< hisilicon‎ | k3

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== Expansions ==
 +
* 4x high-speed UART interfaces
 +
* 2x SPI
 +
* 2x I2C
 +
* USB 2.0 On-The-Go (HS OTG) PHY
 +
* USB 1.1
 +
* 2x MMC/SD/SDIO interface
 +
* 14x GPIOs
 +
* 8 Timers
  
 +
== Graphics ==
 +
The K3V1 integrated graphics engine, although the exact specs are not available. This GPU is most likely a licensed [[Vivante]] core.
 +
 +
* Support QVGA, WQVGA, VGA display resolutions
 +
* Hardware-acceleration video
 +
** Decode: MPEG4, H.263, H.264, and VC-1
 +
*** Rate QCIF/CIF/QVGA/VGA/D1, frame rate up to 30fps
 +
** Encode: MPEG4 and H.263 video encoding
 +
*** QCIF/CIF/QVGA/VGA, frame rate up to 30fps
 +
* 200 KiB Frame Buffer
 +
 +
== Camera ==
 +
* Support 30 million pixel camera, up to 30fps
 +
* Supports up to 8 megapixel CMOS Sensor image input
 +
 +
== Audio ==
 +
* Built-in high-performance audio CODEC
 +
** Sampling frequency support 44.1kHz and 48kHz
 +
** support for sound playback and recording
 +
* High quality stereo playback DAC and 1 channel Voice DAC, 2 channels
 +
** ADC, CODEC support any audio mixing, independent of the amplifier Output gain control
  
 
== Documents ==
 
== Documents ==
 
* [[:File:k3v1 prod brief.pdf|K3V1 Product Brief]]
 
* [[:File:k3v1 prod brief.pdf|K3V1 Product Brief]]

Revision as of 00:14, 6 September 2017

Template:mpu K3V1 is a 32-bit performance ARM microprocessor introduced by HiSilicon in 2008. This chip incorporates a single ARM9 core with Jazelle support operating at 460 MHz (although later models might have supported higher frequency). This chip supports 32-bit or 16-bit DDR memory.

Cache

Main article: ARM9 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$32 KiB
32,768 B
0.0313 MiB
L1I$16 KiB
16,384 B
0.0156 MiB
1x16 KiB4-way set associative 
L1D$16 KiB
16,384 B
0.0156 MiB
1x16 KiB4-way set associative 

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR
Controllers1
Channels1
Width16 bit, 32 bit

Expansions

  • 4x high-speed UART interfaces
  • 2x SPI
  • 2x I2C
  • USB 2.0 On-The-Go (HS OTG) PHY
  • USB 1.1
  • 2x MMC/SD/SDIO interface
  • 14x GPIOs
  • 8 Timers

Graphics

The K3V1 integrated graphics engine, although the exact specs are not available. This GPU is most likely a licensed Vivante core.

  • Support QVGA, WQVGA, VGA display resolutions
  • Hardware-acceleration video
    • Decode: MPEG4, H.263, H.264, and VC-1
      • Rate QCIF/CIF/QVGA/VGA/D1, frame rate up to 30fps
    • Encode: MPEG4 and H.263 video encoding
      • QCIF/CIF/QVGA/VGA, frame rate up to 30fps
  • 200 KiB Frame Buffer

Camera

  • Support 30 million pixel camera, up to 30fps
  • Supports up to 8 megapixel CMOS Sensor image input

Audio

  • Built-in high-performance audio CODEC
    • Sampling frequency support 44.1kHz and 48kHz
    • support for sound playback and recording
  • High quality stereo playback DAC and 1 channel Voice DAC, 2 channels
    • ADC, CODEC support any audio mixing, independent of the amplifier Output gain control

Documents

Facts about "K3V1 - HiSilicon"
has ecc memory supportfalse +
l1$ size32 KiB (32,768 B, 0.0313 MiB) +
l1d$ description4-way set associative +
l1d$ size16 KiB (16,384 B, 0.0156 MiB) +
l1i$ description4-way set associative +
l1i$ size16 KiB (16,384 B, 0.0156 MiB) +
max memory channels1 +
supported memory typeDDR +