From WikiChip
Difference between revisions of "hisilicon/k3/k3v1"
< hisilicon‎ | k3

(Created page with "{{hisilicon title|K3V1}} {{mpu}} '''K3V1''' is a {{arch|32}} performance ARM microprocessor introduced by HiSilicon in 2008. This chip incorporates a single core...")
 
Line 1: Line 1:
 
{{hisilicon title|K3V1}}
 
{{hisilicon title|K3V1}}
−
{{mpu}}
+
{{mpu
 +
|name=K3V1
 +
|no image=Yes
 +
|designer=HiSilicon
 +
|manufacturer=TSMC
 +
|model number=K3V1
 +
|part number=Hi3611
 +
|market=Mobile
 +
|first announced=June, 2008
 +
|first launched=June, 2008
 +
|family=K3
 +
|frequency=460
 +
|isa=ARMv5
 +
|isa family=ARM
 +
|microarch=ARM9
 +
|core name=ARM926EJ-S
 +
|process=0.18 µm
 +
|transistors=200,000,000
 +
|technology=CMOS
 +
|word size=32 bit
 +
|core count=1
 +
|thread count=1
 +
|max cpus=1
 +
|package module 1={{packages/hisilicon/tfbga-460}}
 +
}}
 
'''K3V1''' is a {{arch|32}} performance [[ARM]] microprocessor introduced by [[HiSilicon]] in [[2008]]. This chip incorporates a [[single core|single]] {{armh|ARM9}} core with {{arm|Jazelle}} support operating at 460 MHz (although later models might have supported higher frequency). This chip supports 32-bit or 16-bit DDR memory.
 
'''K3V1''' is a {{arch|32}} performance [[ARM]] microprocessor introduced by [[HiSilicon]] in [[2008]]. This chip incorporates a [[single core|single]] {{armh|ARM9}} core with {{arm|Jazelle}} support operating at 460 MHz (although later models might have supported higher frequency). This chip supports 32-bit or 16-bit DDR memory.

Revision as of 22:57, 5 September 2017

Template:mpu K3V1 is a 32-bit performance ARM microprocessor introduced by HiSilicon in 2008. This chip incorporates a single ARM9 core with Jazelle support operating at 460 MHz (although later models might have supported higher frequency). This chip supports 32-bit or 16-bit DDR memory.

Retrieved from "https://en.wikichip.org/w/index.php?title=hisilicon/k3/k3v1&oldid=63517"