Semiconductor & Computer Engineering
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Difference between revisions of "intel/core i7/i7-2655le"
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| − | '''Core i7-2655LE''' is a {{arch|64}} [[dual-core]] performance embedded mobile [[x86]] microprocessor introduced by [[Intel]] in early 2011. This processor is manufactured on a [[32 nm process]] based on the {{intel|Sandy Bridge|l=arch}} microarchitecture and operates at 2.2 GHz with a [[TDP]] of 25 W and a {{intel|turbo boost}} frequency of up to 2.9 GHz. The i7-2655LE incorporates Intel's {{intel|HD Graphics 3000}} integrated graphics operating at 650 MHz with a burst frequency of 1.2 GHz. This processor supports up to 16 GiB of dual-channel DDR3-1333 memory. | + | '''Core i7-2655LE''' is a {{arch|64}} [[dual-core]] performance embedded mobile [[x86]] microprocessor introduced by [[Intel]] in early 2011. This processor is manufactured on a [[32 nm process]] based on the {{intel|Sandy Bridge|l=arch}} microarchitecture and operates at 2.2 GHz with a [[TDP]] of 25 W and a {{intel|turbo boost}} frequency of up to 2.9 GHz. The i7-2655LE incorporates Intel's {{intel|HD Graphics 3000}} integrated graphics operating at 650 MHz with a burst frequency of 1.2 GHz. This processor supports up to 16 GiB of dual-channel DDR3-1333 ECC memory. |
== Cache == | == Cache == | ||
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|type=DDR3-1333 | |type=DDR3-1333 | ||
|type 2=DDR3-1066 | |type 2=DDR3-1066 | ||
| − | |ecc= | + | |ecc=Yes |
|max mem=16 GiB | |max mem=16 GiB | ||
|controllers=1 | |controllers=1 | ||
Revision as of 16:35, 3 September 2017
Template:mpu Core i7-2655LE is a 64-bit dual-core performance embedded mobile x86 microprocessor introduced by Intel in early 2011. This processor is manufactured on a 32 nm process based on the Sandy Bridge microarchitecture and operates at 2.2 GHz with a TDP of 25 W and a turbo boost frequency of up to 2.9 GHz. The i7-2655LE incorporates Intel's HD Graphics 3000 integrated graphics operating at 650 MHz with a burst frequency of 1.2 GHz. This processor supports up to 16 GiB of dual-channel DDR3-1333 ECC memory.
Cache
- Main article: Sandy Bridge § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options |
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Graphics
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Integrated Graphics Information
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| [Edit] Sandy Bridge (Gen6) Hardware Accelerated Video Capabilities | |||||||
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| Codec | Encode | Decode | |||||
| Profiles | Levels | Max Resolution | Profiles | Levels | Max Resolution | ||
| MPEG-2 (H.262) | ✘ | Main | Main, High | Up to 80 Mbps | |||
| MPEG-4 AVC (H.264) | Main | 4.1 | Up to 40 Mbps | Main, High | 4.1 | Up to 40 Mbps | |
| VC-1 | ✘ | Advanced, Main, Simple | 3, High, Simple | Up to 40 Mbps | |||
Features
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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Facts about "Core i7-2655LE - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Core i7-2655LE - Intel#pcie + |
| device id | 0x116 + |
| has ecc memory support | true + |
| integrated gpu | HD Graphics 3000 + |
| integrated gpu base frequency | 650 MHz (0.65 GHz, 650,000 KHz) + |
| integrated gpu designer | Intel + |
| integrated gpu execution units | 12 + |
| integrated gpu max frequency | 1,200 MHz (1.2 GHz, 1,200,000 KHz) + |
| l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
| l3$ description | 16-way set associative + |
| l3$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
| max memory bandwidth | 19.87 GiB/s (20,346.88 MiB/s, 21.335 GB/s, 21,335.25 MB/s, 0.0194 TiB/s, 0.0213 TB/s) + |
| max memory channels | 2 + |
| supported memory type | DDR3-1333 + and DDR3-1066 + |