Difference between revisions of "intel/core i7ee/i7-2960xm"

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Revision as of 20:30, 2 September 2017

Template:mpu The Core i7-2960XM Extreme Edition was a 64-bit quad-core high-end mobile microprocessor introduced by Intel in late 2011. This chip operated at 2.7 GHz with turbo mode of up to 3.7 GHz for a single core. This chip, which is based on the Sandy Bridge microarchitecture and manufactured in 32 nm process has a TDP of 55 W and supports up to 32 GiB of memory (DDR3).

1 Cache
2 Graphics
3 Memory controller
4 Expansions
5 Features
6 See also

Cache

Main article: Sandy Bridge § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

256 KiB

262,144 B
0.25 MiB

L1I$	128 KiB 131,072 B 0.125 MiB	4x32 KiB	8-way set associative
L1D$	128 KiB 131,072 B 0.125 MiB	4x32 KiB	8-way set associative	write-back

L2$

1 MiB

1,024 KiB
1,048,576 B
9.765625e-4 GiB

		4x256 KiB	8-way set associative	write-back

L3$

8 MiB

8,192 KiB
8,388,608 B
0.00781 GiB

		4x2 MiB	16-way set associative	write-back

Graphics

Integrated Graphic Information
GPU	Intel HD Graphics 3000
Execution Units	12
Displays	2
Frequency	650 MHz 0.65 GHz 650,000 KHz
Max frequency	1300 MHz 1.3 GHz 1,300,000 KHz
Output	DisplayPort, Embedded DisplayPort, HDMI, DVI, SDVO, CRT
DirectX	9, 10, 10.1
OpenGL	3.0
HDMI	1.4
	Intel Quick Sync Video
	Intel InTru 3D
	Intel Insider
	Intel WiDi (Wireless Display)
	Intel Flexible Display Interface (FDI)
	Intel Clear Video

Full AVC/VC1/MPEG2 HW Decode

Memory controller

Integrated Memory Controller
Type	DDR3-1066, DDR3-1333, DDR3-1600
Controllers	1
Channels	2
ECC Support	No
Max bandwidth	25,600 MB/s
Max memory	32,768 MB

Expansions

Template:mpu expansions

Features

Template:mpu features

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Core i7-2960XM Extreme Edition - Intel#package + and Core i7-2960XM Extreme Edition - Intel#pcie +
base frequency	2,700 MHz (2.7 GHz, 2,700,000 kHz) +
bus links	4 +
bus rate	5,000 MT/s (5 GT/s, 5,000,000 kT/s) +
bus type	DMI 2.0 +
chipset	Cougar Point +
clock multiplier	27 +
core count	4 +
core family	6 +
core model	42 +
core name	Sandy Bridge M +
core stepping	D2 +
core voltage (max)	1.52 V (15.2 dV, 152 cV, 1,520 mV) +
core voltage (min)	0.3 V (3 dV, 30 cV, 300 mV) +
cpuid	0x206A7 +
designer	Intel +
device id	0x116 +
die area	216 mm² (0.335 in², 2.16 cm², 216,000,000 µm²) +
family	Core i7EE +
first announced	September 4, 2011 +
first launched	September 4, 2011 +
full page name	intel/core i7ee/i7-2960xm +
has 4g support	true +
has advanced vector extensions	true +
has ecc memory support	false +
has extended page tables support	true +
has feature	Advanced Vector Extensions +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Flex Memory Access +, My WiFi Technology + and Identity Protection Technology +
has intel enhanced speedstep technology	true +
has intel flex memory access support	true +
has intel identity protection technology support	true +
has intel my wifi technology support	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	false +
has second level address translation support	true +
has simultaneous multithreading	true +
has wimax support	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
integrated gpu	HD Graphics 3000 +
integrated gpu base frequency	650 MHz (0.65 GHz, 650,000 KHz) +
integrated gpu designer	Intel +
integrated gpu execution units	12 +
integrated gpu max frequency	1,300 MHz (1.3 GHz, 1,300,000 KHz) +
isa	x86-64 +
isa family	x86 +
l1$ size	256 KiB (262,144 B, 0.25 MiB) +
l1d$ description	8-way set associative +
l1d$ size	128 KiB (131,072 B, 0.125 MiB) +
l1i$ description	8-way set associative +
l1i$ size	128 KiB (131,072 B, 0.125 MiB) +
l2$ description	8-way set associative +
l2$ size	1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ description	16-way set associative +
l3$ size	8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
last order	July 11, 2013 +
last shipment	January 14, 2014 +
ldate	September 4, 2011 +
manufacturer	Intel +
market segment	Mobile +
max cpu count	1 +
max junction temperature	373.15 K (100 °C, 212 °F, 671.67 °R) +
max memory	32,768 MiB (33,554,432 KiB, 34,359,738,368 B, 32 GiB, 0.0313 TiB) +
max memory bandwidth	23.84 GiB/s (24,412.16 MiB/s, 25.598 GB/s, 25,598.005 MB/s, 0.0233 TiB/s, 0.0256 TB/s) +
max memory channels	2 +
max operating temperature	100 °C +
max storage temperature	398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitecture	Sandy Bridge +
min junction temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
min operating temperature	0 °C +
min storage temperature	248.15 K (-25 °C, -13 °F, 446.67 °R) +
model number	i7-2960XM +
name	Core i7-2960XM Extreme +
package	rPGA988B +
part number	FF8062700834603 +
platform	Sandy Bridge M +
power dissipation (idle)	4 W (4,000 mW, 0.00536 hp, 0.004 kW) +
process	32 nm (0.032 μm, 3.2e-5 mm) +
release price	$ 1,096.00 (€ 986.40, £ 887.76, ¥ 113,249.68) +
s-spec	SR02F +
s-spec (qs)	Q1NA +
series	i7-2000 +
smp max ways	1 +
socket	Socket G2 +
supported memory type	DDR3-1600 +, DDR3-1333 + and DDR3-1066 +
tdp	55 W (55,000 mW, 0.0738 hp, 0.055 kW) +
technology	CMOS +
thread count	8 +
transistor count	1,160,000,000 +
turbo frequency (1 core)	3,700 MHz (3.7 GHz, 3,700,000 kHz) +
turbo frequency (2 cores)	3,600 MHz (3.6 GHz, 3,600,000 kHz) +
turbo frequency (3 cores)	3,400 MHz (3.4 GHz, 3,400,000 kHz) +
turbo frequency (4 cores)	3,400 MHz (3.4 GHz, 3,400,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +

@@ Line 67: / Line 67: @@
 == Cache ==
-{{main|intel/microarchitectures/sandy bridge#Memory_Hierarchy|l1=Sandy Bridge § Cache}}
+{{main|intel/microarchitectures/sandy_bridge#Memory_Hierarchy|l1=Sandy Bridge § Cache}}
-{{cache info
+{{cache size
+|l1 cache=256 KiB
 |l1i cache=128 KiB
 |l1i break=4x32 KiB
 |l1i desc=8-way set associative
-|l1i extra=(per core)
 |l1d cache=128 KiB
 |l1d break=4x32 KiB
 |l1d desc=8-way set associative
-|l1d extra=(per core)
+|l1d policy=write-back
 |l2 cache=1 MiB
 |l2 break=4x256 KiB
 |l2 desc=8-way set associative
-|l2 extra=(per core)
+|l2 policy=write-back
 |l3 cache=8 MiB
 |l3 break=4x2 MiB
 |l3 desc=16-way set associative
-|l3 extra=(shared)
+|l3 policy=write-back
 }}

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