Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "intel/core i5/i5-2497m"
| Line 50: | Line 50: | ||
|package module 1={{packages/intel/fcbga-1023}} | |package module 1={{packages/intel/fcbga-1023}} | ||
}} | }} | ||
| + | '''Core i5-2497M''' is a [[dual-core]] mid-range performance mobile [[x86]] microprocessor introduced by mid-[[Intel]] in late [[2011]]. This chip, which is fabricated on a [[32 nm process]] based on the {{intel|Sandy Bridge|l=arch}} microarchitecture, operates at 1.5 GHz with a [[TDP]] of 35 Watts and a {{intel|Turbo Boost}} frequency of up to ? GHz. The i5-2497M incorporates {{intel|HD Graphics 3000}} integrated graphics operating at 350 MHz with a burst frequency of ? GHz and supports up to 16 GiB of dual-channel DDR3-1333 memory. | ||
== Cache == | == Cache == | ||
Revision as of 16:00, 26 August 2017
Template:mpu Core i5-2497M is a dual-core mid-range performance mobile x86 microprocessor introduced by mid-Intel in late 2011. This chip, which is fabricated on a 32 nm process based on the Sandy Bridge microarchitecture, operates at 1.5 GHz with a TDP of 35 Watts and a Turbo Boost frequency of up to ? GHz. The i5-2497M incorporates HD Graphics 3000 integrated graphics operating at 350 MHz with a burst frequency of ? GHz and supports up to 16 GiB of dual-channel DDR3-1333 memory.
Cache
- Main article: Sandy Bridge § Cache
 |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
||||||||||||||||||||||||||||||||||||
|
|||||||||||||||||||||||||||||||||||||
Memory controller
 |
Integrated Memory Controller
|
|||||||||||||
|
||||||||||||||
Expansions
 |
Expansion Options |
||||
|
|||||
Graphics
 |
Integrated Graphics Information
|
|||||||||||||||||||||||||||||||||||||||||||||||||
|
||||||||||||||||||||||||||||||||||||||||||||||||||
| [Edit] Sandy Bridge (Gen6) Hardware Accelerated Video Capabilities | |||||||
|---|---|---|---|---|---|---|---|
| Codec | Encode | Decode | |||||
| Profiles | Levels | Max Resolution | Profiles | Levels | Max Resolution | ||
| MPEG-2 (H.262) | ✘ | Main | Main, High | Up to 80 Mbps | |||
| MPEG-4 AVC (H.264) | Main | 4.1 | Up to 40 Mbps | Main, High | 4.1 | Up to 40 Mbps | |
| VC-1 | ✘ | Advanced, Main, Simple | 3, High, Simple | Up to 40 Mbps | |||
Features
[Edit/Modify Supported Features]
 |
Supported x86 Extensions & Processor Features
|
|
|
|
||
Facts about "Core i5-2497M - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Core i5-2497M - Intel#pcie + |
| device id | 0x116 + |
| has ecc memory support | false + |
| integrated gpu | HD Graphics 3000 + |
| integrated gpu base frequency | 350 MHz (0.35 GHz, 350,000 KHz) + |
| integrated gpu designer | Intel + |
| integrated gpu execution units | 12 + |
| l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
| l3$ description | 12-way set associative + |
| l3$ size | 3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) + |
| max memory bandwidth | 19.87 GiB/s (20,346.88 MiB/s, 21.335 GB/s, 21,335.25 MB/s, 0.0194 TiB/s, 0.0213 TB/s) + |
| max memory channels | 2 + |
| supported memory type | DDR3-1333 + and DDR3-1066 + |