From WikiChip
Difference between revisions of "intel/atom/c3538"
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|bandwidth schan=13.91 GiB/s | |bandwidth schan=13.91 GiB/s | ||
|bandwidth dchan=27.82 GiB/s | |bandwidth dchan=27.82 GiB/s | ||
| + | }} | ||
| + | |||
| + | == Features == | ||
| + | {{x86 features | ||
| + | |real=Yes | ||
| + | |protected=Yes | ||
| + | |smm=Yes | ||
| + | |fpu=Yes | ||
| + | |x8616=Yes | ||
| + | |x8632=Yes | ||
| + | |x8664=Yes | ||
| + | |nx=Yes | ||
| + | |mmx=Yes | ||
| + | |emmx=Yes | ||
| + | |sse=Yes | ||
| + | |sse2=Yes | ||
| + | |sse3=Yes | ||
| + | |ssse3=Yes | ||
| + | |sse41=Yes | ||
| + | |sse42=Yes | ||
| + | |sse4a=No | ||
| + | |avx=No | ||
| + | |avx2=No | ||
| + | |avx512f=No | ||
| + | |avx512cd=No | ||
| + | |avx512er=No | ||
| + | |avx512pf=No | ||
| + | |avx512bw=No | ||
| + | |avx512dq=No | ||
| + | |avx512vl=No | ||
| + | |avx512ifma=No | ||
| + | |avx512vbmi=No | ||
| + | |avx5124fmaps=No | ||
| + | |avx5124vnniw=No | ||
| + | |avx512vpopcntdq=No | ||
| + | |abm=No | ||
| + | |tbm=No | ||
| + | |bmi1=No | ||
| + | |bmi2=No | ||
| + | |fma3=No | ||
| + | |fma4=No | ||
| + | |aes=Yes | ||
| + | |rdrand=Yes | ||
| + | |sha=Yes | ||
| + | |xop=No | ||
| + | |adx=No | ||
| + | |clmul=No | ||
| + | |f16c=No | ||
| + | |tbt1=No | ||
| + | |tbt2=No | ||
| + | |tbmt3=No | ||
| + | |bpt=No | ||
| + | |eist=Yes | ||
| + | |sst=No | ||
| + | |flex=No | ||
| + | |fastmem=No | ||
| + | |ivmd=No | ||
| + | |intelnodecontroller=No | ||
| + | |intelnode=No | ||
| + | |kpt=No | ||
| + | |ptt=No | ||
| + | |intelrunsure=No | ||
| + | |mbe=No | ||
| + | |isrt=No | ||
| + | |sba=No | ||
| + | |mwt=No | ||
| + | |sipp=No | ||
| + | |att=No | ||
| + | |ipt=No | ||
| + | |tsx=No | ||
| + | |txt=No | ||
| + | |ht=No | ||
| + | |vpro=No | ||
| + | |vtx=Yes | ||
| + | |vtd=Yes | ||
| + | |ept=Yes | ||
| + | |mpx=Yes | ||
| + | |sgx=No | ||
| + | |securekey=No | ||
| + | |osguard=No | ||
| + | |3dnow=No | ||
| + | |e3dnow=No | ||
| + | |smartmp=No | ||
| + | |powernow=No | ||
| + | |amdvi=No | ||
| + | |amdv=No | ||
| + | |amdsme=No | ||
| + | |amdtsme=No | ||
| + | |amdsev=No | ||
| + | |rvi=No | ||
| + | |smt=No | ||
| + | |sensemi=No | ||
| + | |xfr=No | ||
}} | }} | ||
Revision as of 08:02, 16 August 2017
Template:mpu Atom C3538 is a 64-bit quad-core ultra-low power x86 microserver system on a chip introduced by Intel in 2017. The C3538, which is manufactured on a 14 nm process, is based on the Goldmont microarchitecture. This chip operates at 2.1 GHz with a TDP of 15 W. The C3538 supports up to a dual-channel of 256 GiB of DDR4-1866 ECC memory. This model is part of Denverton's Network and Enterprise Storage SKUs and come with integrated QuickAssist Technology.
Cache
- Main article: Goldmont § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Features
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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Facts about "Atom C3538 - Intel"
| has ecc memory support | true + |
| has extended page tables support | true + |
| has feature | Advanced Encryption Standard Instruction Set Extension +, Enhanced SpeedStep Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables + and Memory Protection Extensions + |
| has intel enhanced speedstep technology | true + |
| has intel vt-d technology | true + |
| has intel vt-x technology | true + |
| has second level address translation support | true + |
| has x86 advanced encryption standard instruction set extension | true + |
| l1$ size | 224 KiB (229,376 B, 0.219 MiB) + |
| l1d$ description | 6-way set associative + |
| l1d$ size | 96 KiB (98,304 B, 0.0938 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l2$ description | 16-way set associative + |
| l2$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
| max memory bandwidth | 27.82 GiB/s (28,487.68 MiB/s, 29.871 GB/s, 29,871.498 MB/s, 0.0272 TiB/s, 0.0299 TB/s) + |
| max memory channels | 2 + |
| part of | Network and Enterprise Storage SKUs + |
| supported memory type | DDR3L-1600 + and DDR4-1866 + |
| x86/has memory protection extensions | true + |