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Difference between revisions of "renesas/r-car/l1"
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'''R-Car L1''' is a performance embedded SoC for the automotive industry designed by [[Renesas]]. The L1 features a single {{armh|Cortex-A9|l=arch}} core operating at 400 MHz. This chip incorporates [[Imagination]]'s {{imgtec|PowerVR SGX531}} [[GPU]]. This SoC supports up to 1 GiB of DDR3-1066 memory.
 
'''R-Car L1''' is a performance embedded SoC for the automotive industry designed by [[Renesas]]. The L1 features a single {{armh|Cortex-A9|l=arch}} core operating at 400 MHz. This chip incorporates [[Imagination]]'s {{imgtec|PowerVR SGX531}} [[GPU]]. This SoC supports up to 1 GiB of DDR3-1066 memory.
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* '''Note:''' It's unknown if this model was ever actually released.
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== Cache ==
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{{main|arm holdings/microarchitectures/cortex-a9#Memory_Hierarchy|l1=Cortex-A9 § Cache}}
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{{cache size
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|l1 cache=64 KiB
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|l1i cache=32 KiB
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|l1i break=1x32 KiB
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|l1i desc=4-way set associative
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|l1d cache=32 KiB
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|l1d break=1x32 KiB
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|l1d desc=4-way set associative
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}}
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== Memory controller ==
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{{memory controller
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|type=DDR3-1066
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|type 2=DDR2-533
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|ecc=No
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|max mem=1 GiB
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|controllers=1
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|channels=1
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|width=32 bit
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|max bandwidth=1.99 GiB/s
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|bandwidth schan=1.99 GiB/s
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}}
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== Graphics ==
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{{integrated graphics
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| gpu                = PowerVR SGX531
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| designer            = Imagination Technologies
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| execution units    = 1
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| opengl es ver      = 2.0
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}}
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== Features ==
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{{arm features
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|thumb=No
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|thumb2=Yes
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|thumbee=Yes
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|vfpv1=No
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|vfpv2=No
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|vfpv3=Yes
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|vfpv3-d16=No
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|vfpv3-f16=No
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|vfpv4=No
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|vfpv4-d16=No
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|vfpv5=No
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|neon=Yes
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|jazelle=Yes
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|wmmx=No
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|wmmx2=No
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}}

Revision as of 12:55, 21 July 2017

Template:mpu R-Car L1 is a performance embedded SoC for the automotive industry designed by Renesas. The L1 features a single Cortex-A9 core operating at 400 MHz. This chip incorporates Imagination's PowerVR SGX531 GPU. This SoC supports up to 1 GiB of DDR3-1066 memory.

  • Note: It's unknown if this model was ever actually released.

Cache

Main article: Cortex-A9 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$64 KiB
65,536 B
0.0625 MiB
L1I$32 KiB
32,768 B
0.0313 MiB
1x32 KiB4-way set associative 
L1D$32 KiB
32,768 B
0.0313 MiB
1x32 KiB4-way set associative 

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-1066, DDR2-533
Supports ECCNo
Max Mem1 GiB
Controllers1
Channels1
Width32 bit
Max Bandwidth1.99 GiB/s
2,037.76 MiB/s
2.137 GB/s
2,136.746 MB/s
0.00194 TiB/s
0.00214 TB/s
Bandwidth
Single 1.99 GiB/s

Graphics

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUPowerVR SGX531
DesignerImagination Technologies
Execution Units1
Standards
OpenGL ES2.0

Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
Thumb-2Thumb-2 Extension
ThumbEEThumb Execution Environment Extension
VFPv3Vector Floating Point (VFP) v3 Extension
NEONAdvanced SIMD extension
JazelleDirect Bytecode eXecution
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Facts about "R-Car L1 - Renesas"
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has ecc memory supportfalse +
integrated gpuPowerVR SGX531 +
integrated gpu designerImagination Technologies +
integrated gpu execution units1 +
l1$ size64 KiB (65,536 B, 0.0625 MiB) +
l1d$ description4-way set associative +
l1d$ size32 KiB (32,768 B, 0.0313 MiB) +
l1i$ description4-way set associative +
l1i$ size32 KiB (32,768 B, 0.0313 MiB) +
max memory bandwidth1.99 GiB/s (2,037.76 MiB/s, 2.137 GB/s, 2,136.746 MB/s, 0.00194 TiB/s, 0.00214 TB/s) +
max memory channels1 +
supported memory typeDDR3-1066 + and DDR2-533 +