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Difference between revisions of "intel/core i3/i3-7120t"
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{{intel title|Core i3-7120T}} | {{intel title|Core i3-7120T}} | ||
{{mpu | {{mpu | ||
| − | | name | + | |future=Yes |
| − | | no image | + | |name=Core i3-7120T |
| − | + | |no image=Yes | |
| − | + | |designer=Intel | |
| − | + | |manufacturer=Intel | |
| − | | designer | + | |model number=i3-7120T |
| − | | manufacturer | + | |s-spec=SR35Q |
| − | | model number | + | |market=Desktop |
| − | | s-spec | + | |first announced=July, 2017 |
| − | + | |release price=$117.00 | |
| − | | market | + | |family=Core i3 |
| − | | first announced | + | |series=i3-7000 |
| − | + | |locked=Yes | |
| − | + | |frequency=3,500 MHz | |
| − | | release price | + | |bus type=DMI 3.0 |
| − | + | |bus rate=8 GT/s | |
| − | | family | + | |clock multiplier=35 |
| − | | series | + | |isa=x86-64 |
| − | | locked | + | |isa family=x86 |
| − | | frequency | + | |microarch=Kaby Lake |
| − | | bus type | + | |platform=Kaby Lake |
| − | + | |chipset=Sunrise Point | |
| − | | bus rate | + | |chipset 2=Union Point |
| − | | clock multiplier | + | |core name=Kaby Lake S |
| − | + | |core family=6 | |
| − | + | |core model=158 | |
| − | | isa | + | |core stepping=S0 |
| − | | isa | + | |process=14 nm |
| − | | microarch | + | |technology=CMOS |
| − | | platform | + | |word size=64 bit |
| − | | chipset | + | |core count=2 |
| − | | chipset 2 | + | |thread count=4 |
| − | | core name | + | |max cpus=1 |
| − | | core family | + | |max memory=64 GiB |
| − | | core model | + | |v core min=0.55 V |
| − | | core stepping | + | |v core max=1.52 V |
| − | + | |tdp=35 W | |
| − | | process | + | |ctdp down frequency=2,500 MHz |
| − | + | |tjunc min=0 °C | |
| − | | technology | + | |tjunc max=92 °C |
| − | + | |tstorage min=-25 °C | |
| − | + | |tstorage max=125 °C | |
| − | + | |package module 1={{packages/intel/lga-1151}} | |
| − | | word size | ||
| − | | core count | ||
| − | | thread count | ||
| − | | max cpus | ||
| − | | max memory | ||
| − | |||
| − | |||
| − | | v core min | ||
| − | | v core max | ||
| − | |||
| − | | tdp | ||
| − | |||
| − | |||
| − | | ctdp down frequency = 2,500 MHz | ||
| − | | tjunc min | ||
| − | | tjunc max | ||
| − | |||
| − | |||
| − | | tstorage min | ||
| − | | tstorage max | ||
| − | |||
| − | |||
| − | |||
| − | | package module 1 | ||
}} | }} | ||
'''Core i3-7120T''' is a {{arch|64}} [[dual-core]] low-end performance [[x86]] desktop microprocessor introduced by [[Intel]] in early [[2017]]. This chip, which is based on the {{intel|Kaby Lake|l=arch}} microarchitecture, is fabricated on Intel's improved [[14 nm|14 nm+ process]]. This processor, which has a base frequency of 3.5 GHz with a TDP of 35 Watts, supports up to 64 GiB of dual-channel DDR4-2400 memory. The i3-7120T incorporates Intel's {{intel|HD Graphics 630}} [[IGP]] operating at 350 MHz with burst frequency of 1.1 GHz. | '''Core i3-7120T''' is a {{arch|64}} [[dual-core]] low-end performance [[x86]] desktop microprocessor introduced by [[Intel]] in early [[2017]]. This chip, which is based on the {{intel|Kaby Lake|l=arch}} microarchitecture, is fabricated on Intel's improved [[14 nm|14 nm+ process]]. This processor, which has a base frequency of 3.5 GHz with a TDP of 35 Watts, supports up to 64 GiB of dual-channel DDR4-2400 memory. The i3-7120T incorporates Intel's {{intel|HD Graphics 630}} [[IGP]] operating at 350 MHz with burst frequency of 1.1 GHz. | ||
Revision as of 20:22, 14 July 2017
Template:mpu Core i3-7120T is a 64-bit dual-core low-end performance x86 desktop microprocessor introduced by Intel in early 2017. This chip, which is based on the Kaby Lake microarchitecture, is fabricated on Intel's improved 14 nm+ process. This processor, which has a base frequency of 3.5 GHz with a TDP of 35 Watts, supports up to 64 GiB of dual-channel DDR4-2400 memory. The i3-7120T incorporates Intel's HD Graphics 630 IGP operating at 350 MHz with burst frequency of 1.1 GHz.
This model has a configurable TDP-down frequency of 2.5 GHz.
Cache
- Main article: Kaby Lake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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Graphics
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Integrated Graphics Information
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| [Edit] Kaby Lake (Gen9.5) Hardware Accelerated Video Capabilities | |||||||
|---|---|---|---|---|---|---|---|
| Codec | Encode | Decode | |||||
| Profiles | Levels | Max Resolution | Profiles | Levels | Max Resolution | ||
| MPEG-2 (H.262) | Main | High | 1080p (FHD) | Main | Main, High | 1080p (FHD) | |
| MPEG-4 AVC (H.264) | High, Main | 5.1 | 2160p (4K) | Main, High, MVC, Stereo | 5.1 | 2160p (4K) | |
| JPEG/MJPEG | Baseline | - | 16k x 16k | Baseline | Unified | 16k x 16k | |
| HEVC (H.265) | Main, Main 10 | 5.1 | 2160p (4K) | Main, Main 10 | 5.1 | 2160p (4K) | |
| VC-1 | ✘ | Advanced, Main, Simple | 3, High, Simple | 3840x3840 | |||
| VP8 | Unified | Unified | N/A | 0 | Unified | 1080p | |
| VP9 | 0 | 2160p (4K) | 0, 2 | Unified | 2160p (4K) | ||
Features
[Edit/Modify Supported Features]
Die Shot
- See also: Kaby Lake § Die Shot
A die shot of Intel's Kaby Lake dual-core desktop processors:
Facts about "Core i3-7120T - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Core i3-7120T - Intel#io + |
| device id | 0x5912 + |
| has advanced vector extensions | true + |
| has advanced vector extensions 2 | true + |
| has ecc memory support | false + |
| has extended page tables support | true + |
| has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Enhanced SpeedStep Technology +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions +, Software Guard Extensions +, Secure Key Technology +, OS Guard + and Identity Protection Technology + |
| has intel enhanced speedstep technology | true + |
| has intel identity protection technology support | true + |
| has intel secure key technology | true + |
| has intel supervisor mode execution protection | true + |
| has second level address translation support | true + |
| has simultaneous multithreading | true + |
| has transactional synchronization extensions | true + |
| has x86 advanced encryption standard instruction set extension | true + |
| integrated gpu | HD Graphics 630 + |
| integrated gpu base frequency | 350 MHz (0.35 GHz, 350,000 KHz) + |
| integrated gpu designer | Intel + |
| integrated gpu execution units | 24 + |
| integrated gpu max frequency | 1,100 MHz (1.1 GHz, 1,100,000 KHz) + |
| integrated gpu max memory | 65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB) + |
| l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l2$ description | 4-way set associative + |
| l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
| l3$ description | 16-way set associative + |
| l3$ size | 3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) + |
| max memory bandwidth | 35.76 GiB/s (36,618.24 MiB/s, 38.397 GB/s, 38,397.008 MB/s, 0.0349 TiB/s, 0.0384 TB/s) + |
| max memory channels | 2 + |
| max pcie lanes | 16 + |
| supported memory type | DDR3L-1600 + and DDR4-2400 + |
| x86/has memory protection extensions | true + |
| x86/has software guard extensions | true + |